mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-23 16:30:00 +00:00
SSE codegen for vsetcc nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
parent
bc1f989e3c
commit
30a0de94e7
@ -744,6 +744,9 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_sse41_pcmpeqq : GCCBuiltin<"__builtin_ia32_pcmpeqq">,
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Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem, Commutative]>;
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def int_x86_sse42_pcmpgtq : GCCBuiltin<"__builtin_ia32_pcmpgtq">,
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Intrinsic<[llvm_v2i64_ty, llvm_v2i64_ty, llvm_v2i64_ty],
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[IntrNoMem]>;
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def int_x86_sse41_pmaxsb : GCCBuiltin<"__builtin_ia32_pmaxsb128">,
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Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem, Commutative]>;
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@ -620,7 +620,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom);
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setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
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setOperationAction(ISD::SELECT, MVT::v4f32, Custom);
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setOperationAction(ISD::VSETCC, MVT::v4f32, Legal);
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setOperationAction(ISD::VSETCC, MVT::v4f32, Custom);
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}
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if (Subtarget->hasSSE2()) {
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@ -646,11 +646,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
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setOperationAction(ISD::FNEG, MVT::v2f64, Custom);
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setOperationAction(ISD::VSETCC, MVT::v2f64, Legal);
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setOperationAction(ISD::VSETCC, MVT::v16i8, Legal);
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setOperationAction(ISD::VSETCC, MVT::v8i16, Legal);
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setOperationAction(ISD::VSETCC, MVT::v4i32, Legal);
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setOperationAction(ISD::VSETCC, MVT::v2i64, Legal);
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setOperationAction(ISD::VSETCC, MVT::v2f64, Custom);
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setOperationAction(ISD::VSETCC, MVT::v16i8, Custom);
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setOperationAction(ISD::VSETCC, MVT::v8i16, Custom);
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setOperationAction(ISD::VSETCC, MVT::v4i32, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom);
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setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom);
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@ -728,6 +727,10 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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}
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if (Subtarget->hasSSE42()) {
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setOperationAction(ISD::VSETCC, MVT::v2i64, Custom);
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}
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// We want to custom lower some of our intrinsics.
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setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
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@ -4685,6 +4688,113 @@ SDOperand X86TargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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SDOperand X86TargetLowering::LowerVSETCC(SDOperand Op, SelectionDAG &DAG) {
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SDOperand Cond;
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SDOperand Op0 = Op.getOperand(0);
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SDOperand Op1 = Op.getOperand(1);
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SDOperand CC = Op.getOperand(2);
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MVT VT = Op.getValueType();
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ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();
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bool isFP = Op.getOperand(1).getValueType().isFloatingPoint();
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if (isFP) {
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unsigned SSECC = 8;
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unsigned Opc = Op0.getValueType() == MVT::v4f32 ? X86ISD::CMPPS :
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X86ISD::CMPPD;
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bool Swap = false;
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETEQ: SSECC = 0; break;
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case ISD::SETOGT:
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case ISD::SETGT: Swap = true; // Fallthrough
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case ISD::SETLT:
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case ISD::SETOLT: SSECC = 1; break;
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case ISD::SETOGE:
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case ISD::SETGE: Swap = true; // Fallthrough
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case ISD::SETLE:
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case ISD::SETOLE: SSECC = 2; break;
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case ISD::SETUO: SSECC = 3; break;
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case ISD::SETONE:
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case ISD::SETNE: SSECC = 4; break;
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case ISD::SETULE: Swap = true;
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case ISD::SETUGE: SSECC = 5; break;
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case ISD::SETULT: Swap = true;
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case ISD::SETUGT: SSECC = 6; break;
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case ISD::SETO: SSECC = 7; break;
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}
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if (Swap)
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std::swap(Op0, Op1);
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// In the one special case we can't handle, emit two comparisons.
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if (SSECC == 8) {
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SDOperand UNORD, EQ;
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assert(SetCCOpcode == ISD::SETUEQ && "Illegal FP comparison");
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UNORD = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(3, MVT::i8));
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EQ = DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(0, MVT::i8));
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return DAG.getNode(ISD::OR, VT, UNORD, EQ);
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}
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// Handle all other FP comparisons here.
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return DAG.getNode(Opc, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8));
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}
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// We are handling one of the integer comparisons here. Since SSE only has
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// GT and EQ comparisons for integer, swapping operands and multiple
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// operations may be required for some comparisons.
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unsigned Opc = 0, EQOpc = 0, GTOpc = 0;
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bool Swap = false, Invert = false, FlipSigns = false;
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switch (VT.getSimpleVT()) {
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default: break;
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case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break;
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case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break;
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case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break;
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case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break;
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}
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switch (SetCCOpcode) {
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default: break;
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case ISD::SETNE: Invert = true;
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case ISD::SETEQ: Opc = EQOpc; break;
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case ISD::SETLT: Swap = true;
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case ISD::SETGT: Opc = GTOpc; break;
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case ISD::SETGE: Swap = true;
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case ISD::SETLE: Opc = GTOpc; Invert = true; break;
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case ISD::SETULT: Swap = true;
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case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break;
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case ISD::SETUGE: Swap = true;
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case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break;
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}
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if (Swap)
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std::swap(Op0, Op1);
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// Since SSE has no unsigned integer comparisons, we need to flip the sign
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// bits of the inputs before performing those operations.
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if (FlipSigns) {
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MVT EltVT = VT.getVectorElementType();
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SDOperand SignBit = DAG.getConstant(EltVT.getIntegerVTSignBit(), EltVT);
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std::vector<SDOperand> SignBits(VT.getVectorNumElements(), SignBit);
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SDOperand SignVec = DAG.getNode(ISD::BUILD_VECTOR, VT, &SignBits[0],
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SignBits.size());
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Op0 = DAG.getNode(ISD::XOR, VT, Op0, SignVec);
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Op1 = DAG.getNode(ISD::XOR, VT, Op1, SignVec);
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}
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SDOperand Result = DAG.getNode(Opc, VT, Op0, Op1);
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// If the logical-not of the result is required, perform that now.
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if (Invert) {
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MVT EltVT = VT.getVectorElementType();
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SDOperand NegOne = DAG.getConstant(EltVT.getIntegerVTBitMask(), EltVT);
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std::vector<SDOperand> NegOnes(VT.getVectorNumElements(), NegOne);
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SDOperand NegOneV = DAG.getNode(ISD::BUILD_VECTOR, VT, &NegOnes[0],
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NegOnes.size());
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Result = DAG.getNode(ISD::XOR, VT, Result, NegOneV);
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}
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return Result;
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}
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SDOperand X86TargetLowering::LowerSELECT(SDOperand Op, SelectionDAG &DAG) {
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bool addTest = true;
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@ -5728,6 +5838,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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case ISD::FNEG: return LowerFNEG(Op, DAG);
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case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG);
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case ISD::SETCC: return LowerSETCC(Op, DAG);
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case ISD::VSETCC: return LowerVSETCC(Op, DAG);
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case ISD::SELECT: return LowerSELECT(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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case ISD::JumpTable: return LowerJumpTable(Op, DAG);
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@ -5819,6 +5930,16 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD";
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case X86ISD::VSHL: return "X86ISD::VSHL";
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case X86ISD::VSRL: return "X86ISD::VSRL";
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case X86ISD::CMPPD: return "X86ISD::CMPPD";
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case X86ISD::CMPPS: return "X86ISD::CMPPS";
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case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB";
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case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW";
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case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD";
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case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ";
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case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB";
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case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW";
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case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD";
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case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ";
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}
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}
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@ -208,7 +208,14 @@ namespace llvm {
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VZEXT_LOAD,
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// VSHL, VSRL - Vector logical left / right shift.
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VSHL, VSRL
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VSHL, VSRL,
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// CMPPD, CMPPS - Vector double/float comparison.
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CMPPD, CMPPS,
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// PCMP* - Vector integer comparisons.
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PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
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PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ
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};
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}
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@ -521,6 +528,7 @@ namespace llvm {
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SDOperand LowerFNEG(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerFCOPYSIGN(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerVSETCC(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerSELECT(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerBRCOND(SDOperand Op, SelectionDAG &DAG);
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SDOperand LowerMEMSET(SDOperand Op, SelectionDAG &DAG);
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@ -215,6 +215,12 @@ class SS4AIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: Ii8<o, F, outs, ins, asm, pattern>, TA, Requires<[HasSSE41]>;
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// SSE4.2 Instruction Templates:
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//
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// SS428I - SSE 4.2 instructions with T8 prefix.
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class SS428I<bits<8> o, Format F, dag outs, dag ins, string asm,
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list<dag> pattern>
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: I<o, F, outs, ins, asm, pattern>, T8, Requires<[HasSSE42]>;
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// X86-64 Instruction templates...
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//
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@ -20,6 +20,8 @@
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def SDTX86FPShiftOp : SDTypeProfile<1, 2, [ SDTCisSameAs<0, 1>,
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SDTCisFP<0>, SDTCisInt<2> ]>;
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def SDTX86VFCMP : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<1, 2>,
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SDTCisFP<1>, SDTCisVT<3, i8>]>;
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def X86fmin : SDNode<"X86ISD::FMIN", SDTFPBinOp>;
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def X86fmax : SDNode<"X86ISD::FMAX", SDTFPBinOp>;
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@ -53,6 +55,16 @@ def X86vzload : SDNode<"X86ISD::VZEXT_LOAD", SDTLoad,
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[SDNPHasChain, SDNPMayLoad]>;
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def X86vshl : SDNode<"X86ISD::VSHL", SDTIntShiftOp>;
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def X86vshr : SDNode<"X86ISD::VSRL", SDTIntShiftOp>;
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def X86cmpps : SDNode<"X86ISD::CMPPS", SDTX86VFCMP>;
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def X86cmppd : SDNode<"X86ISD::CMPPD", SDTX86VFCMP>;
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def X86pcmpeqb : SDNode<"X86ISD::PCMPEQB", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqw : SDNode<"X86ISD::PCMPEQW", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqd : SDNode<"X86ISD::PCMPEQD", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpeqq : SDNode<"X86ISD::PCMPEQQ", SDTIntBinOp, [SDNPCommutative]>;
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def X86pcmpgtb : SDNode<"X86ISD::PCMPGTB", SDTIntBinOp>;
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def X86pcmpgtw : SDNode<"X86ISD::PCMPGTW", SDTIntBinOp>;
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def X86pcmpgtd : SDNode<"X86ISD::PCMPGTD", SDTIntBinOp>;
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def X86pcmpgtq : SDNode<"X86ISD::PCMPGTQ", SDTIntBinOp>;
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//===----------------------------------------------------------------------===//
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// SSE Complex Patterns
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@ -163,22 +175,6 @@ def PSxLDQ_imm : SDNodeXForm<imm, [{
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return getI32Imm(N->getValue() >> 3);
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}]>;
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def SSE_CC_imm : SDNodeXForm<cond, [{
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unsigned Val;
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switch (N->get()) {
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default: Val = 0; assert(0 && "Unexpected CondCode"); break;
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case ISD::SETOEQ: Val = 0; break;
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case ISD::SETOLT: Val = 1; break;
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case ISD::SETOLE: Val = 2; break;
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case ISD::SETUO: Val = 3; break;
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case ISD::SETONE: Val = 4; break;
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case ISD::SETOGE: Val = 5; break;
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case ISD::SETOGT: Val = 6; break;
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case ISD::SETO: Val = 7; break;
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}
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return getI8Imm(Val);
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}]>;
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// SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to PSHUF*,
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// SHUFP* etc. imm.
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def SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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@ -896,10 +892,10 @@ let Constraints = "$src1 = $dst" in {
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[(set VR128:$dst, (int_x86_sse_cmp_ps VR128:$src1,
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(memop addr:$src), imm:$cc))]>;
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}
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def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), VR128:$src2, cond:$cc)),
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(CMPPSrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
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def : Pat<(v4i32 (vsetcc (v4f32 VR128:$src1), (memop addr:$src2), cond:$cc)),
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(CMPPSrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), VR128:$src2, imm:$cc)),
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(CMPPSrri VR128:$src1, VR128:$src2, imm:$cc)>;
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def : Pat<(v4i32 (X86cmpps (v4f32 VR128:$src1), (memop addr:$src2), imm:$cc)),
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(CMPPSrmi VR128:$src1, addr:$src2, imm:$cc)>;
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// Shuffle and unpack instructions
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let Constraints = "$src1 = $dst" in {
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@ -1725,10 +1721,10 @@ let Constraints = "$src1 = $dst" in {
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[(set VR128:$dst, (int_x86_sse2_cmp_pd VR128:$src1,
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(memop addr:$src), imm:$cc))]>;
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}
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def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), VR128:$src2, cond:$cc)),
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(CMPPDrri VR128:$src1, VR128:$src2, (SSE_CC_imm cond:$cc))>;
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def : Pat<(v2i64 (vsetcc (v2f64 VR128:$src1), (memop addr:$src2), cond:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, (SSE_CC_imm cond:$cc))>;
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def : Pat<(v2i64 (X86cmppd VR128:$src1, VR128:$src2, imm:$cc)),
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(CMPPDrri VR128:$src1, VR128:$src2, imm:$cc)>;
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def : Pat<(v2i64 (X86cmppd VR128:$src1, (memop addr:$src2), imm:$cc)),
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(CMPPDrmi VR128:$src1, addr:$src2, imm:$cc)>;
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// Shuffle and unpack instructions
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let Constraints = "$src1 = $dst" in {
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@ -1994,30 +1990,30 @@ defm PCMPGTB : PDI_binop_rm_int<0x64, "pcmpgtb", int_x86_sse2_pcmpgt_b>;
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defm PCMPGTW : PDI_binop_rm_int<0x65, "pcmpgtw", int_x86_sse2_pcmpgt_w>;
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defm PCMPGTD : PDI_binop_rm_int<0x66, "pcmpgtd", int_x86_sse2_pcmpgt_d>;
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def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), VR128:$src2, SETEQ)),
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def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, VR128:$src2)),
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(PCMPEQBrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), (memop addr:$src2), SETEQ)),
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def : Pat<(v16i8 (X86pcmpeqb VR128:$src1, (memop addr:$src2))),
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(PCMPEQBrm VR128:$src1, addr:$src2)>;
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def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), VR128:$src2, SETEQ)),
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def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, VR128:$src2)),
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(PCMPEQWrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), (memop addr:$src2), SETEQ)),
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def : Pat<(v8i16 (X86pcmpeqw VR128:$src1, (memop addr:$src2))),
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(PCMPEQWrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), VR128:$src2, SETEQ)),
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def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, VR128:$src2)),
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||||
(PCMPEQDrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), (memop addr:$src2), SETEQ)),
|
||||
def : Pat<(v4i32 (X86pcmpeqd VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPEQDrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), VR128:$src2, SETGT)),
|
||||
def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, VR128:$src2)),
|
||||
(PCMPGTBrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v16i8 (vsetcc (v16i8 VR128:$src1), (memop addr:$src2), SETGT)),
|
||||
def : Pat<(v16i8 (X86pcmpgtb VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPGTBrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), VR128:$src2, SETGT)),
|
||||
def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, VR128:$src2)),
|
||||
(PCMPGTWrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v8i16 (vsetcc (v8i16 VR128:$src1), (memop addr:$src2), SETGT)),
|
||||
def : Pat<(v8i16 (X86pcmpgtw VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPGTWrm VR128:$src1, addr:$src2)>;
|
||||
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), VR128:$src2, SETGT)),
|
||||
def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, VR128:$src2)),
|
||||
(PCMPGTDrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v4i32 (vsetcc (v4i32 VR128:$src1), (memop addr:$src2), SETGT)),
|
||||
def : Pat<(v4i32 (X86pcmpgtd VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPGTDrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
|
||||
@ -3258,6 +3254,11 @@ defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
|
||||
defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
|
||||
int_x86_sse41_pmaxuw, 1>;
|
||||
|
||||
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
|
||||
(PCMPEQQrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPEQQrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
|
||||
/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
@ -3555,3 +3556,30 @@ def PTESTrm : SS48I<0x17, MRMSrcMem, (outs), (ins VR128:$src1, i128mem:$src2),
|
||||
def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
|
||||
"movntdqa\t{$src, $dst|$dst, $src}",
|
||||
[(set VR128:$dst, (int_x86_sse41_movntdqa addr:$src))]>;
|
||||
|
||||
/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
|
||||
let Constraints = "$src1 = $dst" in {
|
||||
multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
|
||||
Intrinsic IntId128, bit Commutable = 0> {
|
||||
def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
|
||||
(ins VR128:$src1, VR128:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
|
||||
OpSize {
|
||||
let isCommutable = Commutable;
|
||||
}
|
||||
def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
|
||||
(ins VR128:$src1, i128mem:$src2),
|
||||
!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set VR128:$dst,
|
||||
(IntId128 VR128:$src1,
|
||||
(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
|
||||
}
|
||||
}
|
||||
|
||||
defm PCMPGTQ : SS41I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
|
||||
|
||||
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
|
||||
(PCMPGTQrr VR128:$src1, VR128:$src2)>;
|
||||
def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
|
||||
(PCMPGTQrm VR128:$src1, addr:$src2)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user