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[SystemZ] Use RXSBG
Extend the previous R.SBG patches to handle XORs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186570 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -241,9 +241,9 @@ class SystemZDAGToDAGISel : public SelectionDAGISel {
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// Return the selected node on success, otherwise return null.
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SDNode *tryRISBGZero(SDNode *N);
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// Try to use RISBG or ROSBG to implement OR node N. Return the selected
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// node on success, otherwise return null.
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SDNode *tryRISBGOrROSBG(SDNode *N);
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// Try to use RISBG or Opcode to implement OR or XOR node N.
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// Return the selected node on success, otherwise return null.
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SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
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// If Op0 is null, then Node is a constant that can be loaded using:
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//
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@ -799,8 +799,8 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
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return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
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}
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SDNode *SystemZDAGToDAGISel::tryRISBGOrROSBG(SDNode *N) {
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// Try treating each operand of N as the second operand of RISBG or ROSBG
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SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
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// Try treating each operand of N as the second operand of the RxSBG
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// and see which goes deepest.
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RxSBGOperands RxSBG[] = { N->getOperand(0), N->getOperand(1) };
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unsigned Count[] = { 0, 0 };
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@ -817,15 +817,14 @@ SDNode *SystemZDAGToDAGISel::tryRISBGOrROSBG(SDNode *N) {
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SDValue Op0 = N->getOperand(I ^ 1);
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// Prefer IC for character insertions from memory.
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if ((RxSBG[I].Mask & 0xff) == 0)
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if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
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if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
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if (Load->getMemoryVT() == MVT::i8)
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return 0;
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// See whether we can avoid an AND in the first operand by converting
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// ROSBG to RISBG.
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unsigned Opcode = SystemZ::ROSBG;
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if (detectOrAndInsertion(Op0, RxSBG[I].Mask))
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if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask))
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Opcode = SystemZ::RISBG;
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EVT VT = N->getValueType(0);
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@ -913,9 +912,14 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
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switch (Opcode) {
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case ISD::OR:
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if (Node->getOperand(1).getOpcode() != ISD::Constant)
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ResNode = tryRISBGOrROSBG(Node);
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// Fall through.
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ResNode = tryRxSBG(Node, SystemZ::ROSBG);
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goto or_xor;
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case ISD::XOR:
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if (Node->getOperand(1).getOpcode() != ISD::Constant)
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ResNode = tryRxSBG(Node, SystemZ::RXSBG);
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// Fall through.
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or_xor:
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// If this is a 64-bit operation in which both 32-bit halves are nonzero,
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// split the operation into two.
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if (!ResNode && Node->getValueType(0) == MVT::i64)
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@ -931,7 +935,8 @@ SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
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case ISD::ROTL:
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case ISD::SHL:
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case ISD::SRL:
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ResNode = tryRISBGZero(Node);
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if (!ResNode)
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ResNode = tryRISBGZero(Node);
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break;
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case ISD::Constant:
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112
test/CodeGen/SystemZ/rxsbg-01.ll
Normal file
112
test/CodeGen/SystemZ/rxsbg-01.ll
Normal file
@ -0,0 +1,112 @@
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; Test sequences that can use RXSBG.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test the simple case.
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: rxsbg %r2, %r3, 59, 59, 0
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; CHECK: br %r14
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%andb = and i32 %b, 16
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%xor = xor i32 %a, %andb
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ret i32 %xor
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}
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; ...and again with i64.
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: rxsbg %r2, %r3, 59, 59, 0
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; CHECK: br %r14
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%andb = and i64 %b, 16
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%xor = xor i64 %a, %andb
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ret i64 %xor
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}
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; Test a case where wraparound is needed.
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define i32 @f3(i32 %a, i32 %b) {
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; CHECK-LABEL: f3:
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; CHECK: rxsbg %r2, %r3, 63, 60, 0
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; CHECK: br %r14
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%andb = and i32 %b, -7
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%xor = xor i32 %a, %andb
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ret i32 %xor
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}
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; ...and again with i64.
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define i64 @f4(i64 %a, i64 %b) {
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; CHECK-LABEL: f4:
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; CHECK: rxsbg %r2, %r3, 63, 60, 0
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; CHECK: br %r14
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%andb = and i64 %b, -7
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%xor = xor i64 %a, %andb
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ret i64 %xor
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}
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; Test a case with just a shift.
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define i32 @f6(i32 %a, i32 %b) {
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; CHECK-LABEL: f6:
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; CHECK: rxsbg %r2, %r3, 32, 51, 12
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; CHECK: br %r14
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%shlb = shl i32 %b, 12
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%xor = xor i32 %a, %shlb
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ret i32 %xor
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}
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; ...and again with i64.
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define i64 @f7(i64 %a, i64 %b) {
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; CHECK-LABEL: f7:
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; CHECK: rxsbg %r2, %r3, 0, 51, 12
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; CHECK: br %r14
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%shlb = shl i64 %b, 12
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%xor = xor i64 %a, %shlb
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ret i64 %xor
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}
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; Test a case with just a rotate (using XOR for the rotate combination too,
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; to test that this kind of rotate does get recognised by the target-
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; independent code). This can't use RXSBG.
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define i32 @f8(i32 %a, i32 %b) {
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; CHECK-LABEL: f8:
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; CHECK: rll {{%r[0-5]}}
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; CHECK: xr {{%r[0-5]}}
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; CHECK: br %r14
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%shlb = shl i32 %b, 30
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%shrb = lshr i32 %b, 2
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%rotlb = xor i32 %shlb, %shrb
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%xor = xor i32 %a, %rotlb
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ret i32 %xor
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}
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; ...and again with i64, which can use RXSBG for the rotate.
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define i64 @f9(i64 %a, i64 %b) {
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; CHECK-LABEL: f9:
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; CHECK: rxsbg %r2, %r3, 0, 63, 47
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; CHECK: br %r14
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%shlb = shl i64 %b, 47
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%shrb = lshr i64 %b, 17
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%rotlb = xor i64 %shlb, %shrb
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%xor = xor i64 %a, %rotlb
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ret i64 %xor
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}
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; Test a case with a shift and AND.
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define i32 @f10(i32 %a, i32 %b) {
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; CHECK-LABEL: f10:
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; CHECK: rxsbg %r2, %r3, 56, 59, 4
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; CHECK: br %r14
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%shlb = shl i32 %b, 4
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%andb = and i32 %shlb, 240
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%xor = xor i32 %a, %andb
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ret i32 %xor
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}
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; ...and again with i64.
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define i64 @f11(i64 %a, i64 %b) {
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; CHECK-LABEL: f11:
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; CHECK: rxsbg %r2, %r3, 56, 59, 4
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; CHECK: br %r14
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%shlb = shl i64 %b, 4
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%andb = and i64 %shlb, 240
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%xor = xor i64 %a, %andb
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ret i64 %xor
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}
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