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Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19689 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -370,7 +370,7 @@ namespace {
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void EmitFoldedLoad(SDOperand Op, X86AddressMode &AM);
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bool TryToFoldLoadOpStore(SDNode *Node);
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bool EmitDoubleShift(SDOperand Op1, SDOperand Op2, unsigned DestReg);
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bool EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg);
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void EmitCMP(SDOperand LHS, SDOperand RHS, bool isOnlyUse);
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bool EmitBranchCC(MachineBasicBlock *Dest, SDOperand Chain, SDOperand Cond);
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void EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
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@ -1142,11 +1142,11 @@ void ISel::EmitFoldedLoad(SDOperand Op, X86AddressMode &AM) {
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assert(0 && "Load emitted more than once!");
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}
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// EmitDoubleShift - Pattern match the expression (Op1|Op2), where we know that
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// op1 and op2 are i32 values with one use each (the or). If we can form a SHLD
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// or SHRD, emit the instruction (generating the value into DestReg) and return
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// true.
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bool ISel::EmitDoubleShift(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
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// EmitOrOpOp - Pattern match the expression (Op1|Op2), where we know that op1
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// and op2 are i8/i16/i32 values with one use each (the or). If we can form a
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// SHLD or SHRD, emit the instruction (generating the value into DestReg) and
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// return true.
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bool ISel::EmitOrOpOp(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
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if (Op1.getOpcode() == ISD::SHL && Op2.getOpcode() == ISD::SRL) {
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// good!
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} else if (Op2.getOpcode() == ISD::SHL && Op1.getOpcode() == ISD::SRL) {
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@ -1160,10 +1160,12 @@ bool ISel::EmitDoubleShift(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
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SDOperand ShrVal = Op2.getOperand(0);
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SDOperand ShrAmt = Op2.getOperand(1);
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unsigned RegSize = MVT::getSizeInBits(Op1.getValueType());
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// Find out if ShrAmt = 32-ShlAmt or ShlAmt = 32-ShrAmt.
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if (ShlAmt.getOpcode() == ISD::SUB && ShlAmt.getOperand(1) == ShrAmt)
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if (ConstantSDNode *SubCST = dyn_cast<ConstantSDNode>(ShlAmt.getOperand(0)))
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if (SubCST->getValue() == 32) {
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if (SubCST->getValue() == RegSize && RegSize != 8) {
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// (A >> ShrAmt) | (B << (32-ShrAmt)) ==> SHRD A, B, ShrAmt
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unsigned AReg, BReg;
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if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
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@ -1175,13 +1177,14 @@ bool ISel::EmitDoubleShift(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
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}
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unsigned ShAmt = SelectExpr(ShrAmt);
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BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
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BuildMI(BB, X86::SHRD32rrCL,2,DestReg).addReg(AReg).addReg(BReg);
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unsigned Opc = RegSize == 16 ? X86::SHRD16rrCL : X86::SHRD32rrCL;
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BuildMI(BB, Opc, 2, DestReg).addReg(AReg).addReg(BReg);
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return true;
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}
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if (ShrAmt.getOpcode() == ISD::SUB && ShrAmt.getOperand(1) == ShlAmt)
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if (ConstantSDNode *SubCST = dyn_cast<ConstantSDNode>(ShrAmt.getOperand(0)))
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if (SubCST->getValue() == 32) {
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if (SubCST->getValue() == RegSize && RegSize != 8) {
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// (A << ShlAmt) | (B >> (32-ShlAmt)) ==> SHLD A, B, ShrAmt
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unsigned AReg, BReg;
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if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
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@ -1193,14 +1196,15 @@ bool ISel::EmitDoubleShift(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
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}
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unsigned ShAmt = SelectExpr(ShlAmt);
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BuildMI(BB, X86::MOV8rr, 1, X86::CL).addReg(ShAmt);
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BuildMI(BB, X86::SHLD32rrCL,2,DestReg).addReg(AReg).addReg(BReg);
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unsigned Opc = RegSize == 16 ? X86::SHLD16rrCL : X86::SHLD32rrCL;
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BuildMI(BB, Opc, 2, DestReg).addReg(AReg).addReg(BReg);
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return true;
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}
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if (ConstantSDNode *ShrCst = dyn_cast<ConstantSDNode>(ShrAmt))
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if (ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(ShlAmt))
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if (ShrCst->getValue() < 32 && ShlCst->getValue() < 32) {
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if (ShrCst->getValue() == 32-ShlCst->getValue()) {
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if (ShrCst->getValue() < RegSize && ShlCst->getValue() < RegSize) {
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if (ShrCst->getValue() == RegSize-ShlCst->getValue() && RegSize != 8) {
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// (A >> 5) | (B << 27) --> SHRD A, B, 5
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unsigned AReg, BReg;
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if (getRegPressure(ShlVal) > getRegPressure(ShrVal)) {
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@ -1210,7 +1214,8 @@ bool ISel::EmitDoubleShift(SDOperand Op1, SDOperand Op2, unsigned DestReg) {
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BReg = SelectExpr(ShlVal);
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AReg = SelectExpr(ShrVal);
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}
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BuildMI(BB, X86::SHRD32rri8, 3, DestReg).addReg(AReg).addReg(BReg)
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unsigned Opc = RegSize == 16 ? X86::SHRD16rri8 : X86::SHRD32rri8;
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BuildMI(BB, Opc, 3, DestReg).addReg(AReg).addReg(BReg)
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.addImm(ShrCst->getValue());
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return true;
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}
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@ -1737,9 +1742,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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Op0 = Node->getOperand(0);
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Op1 = Node->getOperand(1);
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if (Node->getOpcode() == ISD::OR && N.getValueType() == MVT::i32 &&
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Op0.hasOneUse() && Op1.hasOneUse()) // Match SHLD and SHRD.
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if (EmitDoubleShift(Op0, Op1, Result))
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if (Node->getOpcode() == ISD::OR && Op0.hasOneUse() && Op1.hasOneUse())
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if (EmitOrOpOp(Op0, Op1, Result)) // Match SHLD, SHRD, and rotates.
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return Result;
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if (Node->getOpcode() == ISD::SUB)
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