mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-25 00:29:20 +00:00
Change the order of tBX's operands so that the predicate operands come after the
target register, matching BX. I filed this bug because I was confused at first: PR10007 - ARM branch instructions have inconsistent predicate operand placement <http://llvm.org/bugs/show_bug.cgi?id=10007> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132041 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
8f161c3a95
commit
328634598f
@ -369,7 +369,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
||||
let Inst{2-0} = 0b000;
|
||||
}
|
||||
|
||||
def tBX : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm", []>,
|
||||
def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
|
||||
T1Special<{1,1,0,?}> {
|
||||
// A6.2.3 & A8.6.25
|
||||
bits<4> Rm;
|
||||
|
@ -489,15 +489,24 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
|
||||
|
||||
// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
|
||||
if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
|
||||
if (Opcode != ARM::tBRIND) {
|
||||
if (Opcode == ARM::tBLXr_r9) {
|
||||
// Handling the two predicate operands before the reg operand.
|
||||
if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
|
||||
return false;
|
||||
NumOpsAdded += 2;
|
||||
}
|
||||
|
||||
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
|
||||
getT1Rm(insn))));
|
||||
NumOpsAdded += 1;
|
||||
|
||||
if (Opcode == ARM::tBX) {
|
||||
// Handling the two predicate operands after the reg operand.
|
||||
if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
|
||||
return false;
|
||||
NumOpsAdded += 2;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user