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Rename tBX_Rm to tBX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -369,9 +369,8 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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let Inst{2-0} = 0b000;
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}
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def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
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[/* for disassembly only */]>,
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T1Special<{1,1,0,?}> {
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def tBX : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm", []>,
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T1Special<{1,1,0,?}> {
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// A6.2.3 & A8.6.25
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bits<4> Rm;
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let Inst{6-3} = Rm;
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@ -476,8 +476,8 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
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// tADDhirr: Rd Rd(TIED_TO) Rm
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// tCMPhir: Rd Rm
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// tMOVr, tMOVgpr2gpr, tMOVgpr2tgpr, tMOVtgpr2gpr: Rd|tRd Rm|tRn
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// tBX: Rm
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// tBX_RET: 0 operand
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// tBX_RET_vararg: Rm
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// tBLXr_r9: Rm
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// tBRIND: Rm
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static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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@ -488,7 +488,7 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
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return true;
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// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
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if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX_Rm || Opcode==ARM::tBRIND) {
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if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
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if (Opcode != ARM::tBRIND) {
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// Handling the two predicate operands before the reg operand.
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if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
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