mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-02 10:33:53 +00:00
Rename tBX_Rm to tBX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132040 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
b36c1ae6d5
commit
8f161c3a95
@ -369,9 +369,8 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
|
||||
let Inst{2-0} = 0b000;
|
||||
}
|
||||
|
||||
def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
|
||||
[/* for disassembly only */]>,
|
||||
T1Special<{1,1,0,?}> {
|
||||
def tBX : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm", []>,
|
||||
T1Special<{1,1,0,?}> {
|
||||
// A6.2.3 & A8.6.25
|
||||
bits<4> Rm;
|
||||
let Inst{6-3} = Rm;
|
||||
|
@ -476,8 +476,8 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
|
||||
// tADDhirr: Rd Rd(TIED_TO) Rm
|
||||
// tCMPhir: Rd Rm
|
||||
// tMOVr, tMOVgpr2gpr, tMOVgpr2tgpr, tMOVtgpr2gpr: Rd|tRd Rm|tRn
|
||||
// tBX: Rm
|
||||
// tBX_RET: 0 operand
|
||||
// tBX_RET_vararg: Rm
|
||||
// tBLXr_r9: Rm
|
||||
// tBRIND: Rm
|
||||
static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
|
||||
@ -488,7 +488,7 @@ static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
|
||||
return true;
|
||||
|
||||
// BX/BLX/tBRIND (indirect branch, i.e, mov pc, Rm) has 1 reg operand: Rm.
|
||||
if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX_Rm || Opcode==ARM::tBRIND) {
|
||||
if (Opcode==ARM::tBLXr_r9 || Opcode==ARM::tBX || Opcode==ARM::tBRIND) {
|
||||
if (Opcode != ARM::tBRIND) {
|
||||
// Handling the two predicate operands before the reg operand.
|
||||
if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
|
||||
|
Loading…
x
Reference in New Issue
Block a user