mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Rename load/store instructions to include an RI suffix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24784 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
84e2abf116
commit
331355cf7d
@ -41,12 +41,10 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
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void SparcV8RegisterInfo::
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void SparcV8RegisterInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, int FrameIdx,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *rc) const {
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const TargetRegisterClass *RC) const {
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const TargetRegisterClass *RC = getClass(SrcReg);
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
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if (RC == V8::IntRegsRegisterClass)
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if (RC == V8::IntRegsRegisterClass)
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BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
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BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
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.addReg (SrcReg);
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.addReg (SrcReg);
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else if (RC == V8::FPRegsRegisterClass)
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else if (RC == V8::FPRegsRegisterClass)
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BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
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BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
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@ -61,10 +59,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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void SparcV8RegisterInfo::
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void SparcV8RegisterInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FrameIdx,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *rc) const {
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const TargetRegisterClass *RC) const {
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const TargetRegisterClass *RC = getClass(DestReg);
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if (RC == V8::IntRegsRegisterClass)
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if (RC == V8::IntRegsRegisterClass)
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BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
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BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
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else if (RC == V8::FPRegsRegisterClass)
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else if (RC == V8::FPRegsRegisterClass)
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BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
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BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
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.addSImm (0);
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.addSImm (0);
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@ -372,7 +372,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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assert (IAR != IAREnd
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assert (IAR != IAREnd
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&& "About to dereference past end of IncomingArgRegs");
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&& "About to dereference past end of IncomingArgRegs");
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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ArgOffset += 4;
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ArgOffset += 4;
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}
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}
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// Reset the pointers now that we're done.
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// Reset the pointers now that we're done.
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@ -392,7 +392,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
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BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
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} else {
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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} else if (getClassB (A.getType ()) == cFloat) {
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} else if (getClassB (A.getType ()) == cFloat) {
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@ -403,7 +403,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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assert (IAR != IAREnd
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assert (IAR != IAREnd
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&& "About to dereference past end of IncomingArgRegs");
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&& "About to dereference past end of IncomingArgRegs");
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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} else {
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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@ -418,19 +418,19 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
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unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
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int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
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int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
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if (ArgOffset < 92 && IAR != IAREnd) {
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if (ArgOffset < 92 && IAR != IAREnd) {
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
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} else {
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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if (ArgOffset < 92 && IAR != IAREnd) {
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if (ArgOffset < 92 && IAR != IAREnd) {
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
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} else {
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
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BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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@ -442,7 +442,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
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BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
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} else {
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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// ...then do the second half
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// ...then do the second half
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@ -452,7 +452,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
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BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
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} else {
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} else {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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} else {
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} else {
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@ -644,7 +644,7 @@ void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
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BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
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BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
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.addReg (TempReg);
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.addReg (TempReg);
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unsigned TempReg2 = makeAnotherReg (newTy);
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unsigned TempReg2 = makeAnotherReg (newTy);
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BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::LDri, 3, TempReg2).addFrameIndex (FI).addSImm (0);
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emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
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emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
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}
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}
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@ -698,7 +698,7 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
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// it using ldf into a floating point register. then do fitos.
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// it using ldf into a floating point register. then do fitos.
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unsigned TmpReg = makeAnotherReg (newTy);
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unsigned TmpReg = makeAnotherReg (newTy);
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
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BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (SrcReg);
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.addReg (SrcReg);
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BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
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BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
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@ -720,7 +720,7 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
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unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
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unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
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unsigned TmpReg = makeAnotherReg (newTy);
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unsigned TmpReg = makeAnotherReg (newTy);
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int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
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int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
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BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
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BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
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.addReg (SrcReg);
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.addReg (SrcReg);
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BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
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BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
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BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
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@ -774,22 +774,22 @@ void V8ISel::visitLoadInst(LoadInst &I) {
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switch (getClassB (I.getType ())) {
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switch (getClassB (I.getType ())) {
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case cByte:
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case cByte:
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if (I.getType ()->isSigned ())
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if (I.getType ()->isSigned ())
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BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDSBri, 2, DestReg).addReg (PtrReg).addSImm(0);
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else
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else
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BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDUBri, 2, DestReg).addReg (PtrReg).addSImm(0);
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return;
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return;
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case cShort:
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case cShort:
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if (I.getType ()->isSigned ())
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if (I.getType ()->isSigned ())
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BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDSHri, 2, DestReg).addReg (PtrReg).addSImm(0);
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else
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else
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BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDUHri, 2, DestReg).addReg (PtrReg).addSImm(0);
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return;
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return;
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case cInt:
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case cInt:
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BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
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return;
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return;
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case cLong:
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case cLong:
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BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
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BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (PtrReg).addSImm(4);
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return;
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return;
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case cFloat:
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case cFloat:
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BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
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BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
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@ -810,17 +810,17 @@ void V8ISel::visitStoreInst(StoreInst &I) {
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unsigned PtrReg = getReg (I.getOperand (1));
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unsigned PtrReg = getReg (I.getOperand (1));
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switch (getClassB (SrcVal->getType ())) {
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switch (getClassB (SrcVal->getType ())) {
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case cByte:
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case cByte:
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BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STBri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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return;
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case cShort:
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case cShort:
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BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STHri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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return;
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case cInt:
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case cInt:
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BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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return;
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return;
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case cLong:
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case cLong:
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BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
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BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
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return;
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return;
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case cFloat:
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case cFloat:
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BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
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@ -879,7 +879,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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"About to dereference past end of OutgoingArgRegs");
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
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BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
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} else {
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} else {
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (ArgReg);
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.addReg (ArgReg);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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@ -892,7 +892,7 @@ void V8ISel::visitCallInst(CallInst &I) {
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BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
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BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
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assert (OAR != OAREnd &&
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assert (OAR != OAREnd &&
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"About to dereference past end of OutgoingArgRegs");
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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} else {
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} else {
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BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (ArgReg);
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.addReg (ArgReg);
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@ -909,22 +909,22 @@ void V8ISel::visitCallInst(CallInst &I) {
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if (ArgOffset < 92 && OAR != OAREnd) {
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if (ArgOffset < 92 && OAR != OAREnd) {
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assert (OAR != OAREnd &&
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assert (OAR != OAREnd &&
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"About to dereference past end of OutgoingArgRegs");
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
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} else {
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} else {
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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unsigned TempReg = makeAnotherReg (Type::IntTy);
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BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
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BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
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BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
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.addReg (TempReg);
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.addReg (TempReg);
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}
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}
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ArgOffset += 4;
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ArgOffset += 4;
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if (ArgOffset < 92 && OAR != OAREnd) {
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if (ArgOffset < 92 && OAR != OAREnd) {
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assert (OAR != OAREnd &&
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assert (OAR != OAREnd &&
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"About to dereference past end of OutgoingArgRegs");
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"About to dereference past end of OutgoingArgRegs");
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BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
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BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (4);
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} else {
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} else {
|
||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (TempReg);
|
.addReg (TempReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -935,7 +935,7 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
|
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
|
||||||
} else {
|
} else {
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (ArgReg);
|
.addReg (ArgReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -945,7 +945,7 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
|
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
|
||||||
} else {
|
} else {
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (ArgReg+1);
|
.addReg (ArgReg+1);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -1756,7 +1756,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
|
|||||||
unsigned DestReg = getReg (CI.getOperand(1));
|
unsigned DestReg = getReg (CI.getOperand(1));
|
||||||
unsigned Tmp = makeAnotherReg(Type::IntTy);
|
unsigned Tmp = makeAnotherReg(Type::IntTy);
|
||||||
BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
|
BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
|
||||||
BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
|
BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1767,7 +1767,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
|
|||||||
case Intrinsic::vacopy: {
|
case Intrinsic::vacopy: {
|
||||||
// Copy the va_list ptr (arg1) to the result.
|
// Copy the va_list ptr (arg1) to the result.
|
||||||
unsigned DestReg = getReg (CI.getOperand(1)), SrcReg = getReg (CI.getOperand (2));
|
unsigned DestReg = getReg (CI.getOperand(1)), SrcReg = getReg (CI.getOperand (2));
|
||||||
BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
|
BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1778,21 +1778,21 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
|
|||||||
unsigned DestReg = getReg (I);
|
unsigned DestReg = getReg (I);
|
||||||
unsigned Size;
|
unsigned Size;
|
||||||
unsigned VAList = makeAnotherReg(Type::IntTy);
|
unsigned VAList = makeAnotherReg(Type::IntTy);
|
||||||
BuildMI(BB, V8::LD, 2, VAList).addReg(VAListPtr).addSImm(0);
|
BuildMI(BB, V8::LDri, 2, VAList).addReg(VAListPtr).addSImm(0);
|
||||||
|
|
||||||
switch (I.getType ()->getTypeID ()) {
|
switch (I.getType ()->getTypeID ()) {
|
||||||
case Type::PointerTyID:
|
case Type::PointerTyID:
|
||||||
case Type::UIntTyID:
|
case Type::UIntTyID:
|
||||||
case Type::IntTyID:
|
case Type::IntTyID:
|
||||||
Size = 4;
|
Size = 4;
|
||||||
BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, DestReg).addReg (VAList).addSImm (0);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case Type::ULongTyID:
|
case Type::ULongTyID:
|
||||||
case Type::LongTyID:
|
case Type::LongTyID:
|
||||||
Size = 8;
|
Size = 8;
|
||||||
BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, DestReg).addReg (VAList).addSImm (0);
|
||||||
BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (VAList).addSImm (4);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case Type::DoubleTyID: {
|
case Type::DoubleTyID: {
|
||||||
@ -1801,10 +1801,10 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
|
|||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
unsigned TempReg2 = makeAnotherReg (Type::IntTy);
|
unsigned TempReg2 = makeAnotherReg (Type::IntTy);
|
||||||
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addReg (VAList).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, TempReg).addReg (VAList).addSImm (0);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg2).addReg (VAList).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, TempReg2).addReg (VAList).addSImm (4);
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
|
||||||
BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -1817,6 +1817,6 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
|
|||||||
}
|
}
|
||||||
unsigned tmp = makeAnotherReg(Type::IntTy);
|
unsigned tmp = makeAnotherReg(Type::IntTy);
|
||||||
BuildMI (BB, V8::ADDri, 2, tmp).addReg(VAList).addSImm(Size);
|
BuildMI (BB, V8::ADDri, 2, tmp).addReg(VAList).addSImm(Size);
|
||||||
BuildMI(BB, V8::ST, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
|
BuildMI(BB, V8::STri, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -372,7 +372,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
|||||||
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||||
assert (IAR != IAREnd
|
assert (IAR != IAREnd
|
||||||
&& "About to dereference past end of IncomingArgRegs");
|
&& "About to dereference past end of IncomingArgRegs");
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
}
|
}
|
||||||
// Reset the pointers now that we're done.
|
// Reset the pointers now that we're done.
|
||||||
@ -392,7 +392,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
|||||||
BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
|
BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
|
||||||
} else {
|
} else {
|
||||||
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||||
BuildMI (BB, V8::LD, 3, ArgReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 3, ArgReg).addFrameIndex (FI).addSImm (0);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
} else if (getClassB (A.getType ()) == cFloat) {
|
} else if (getClassB (A.getType ()) == cFloat) {
|
||||||
@ -403,7 +403,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
|||||||
int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
|
int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
|
||||||
assert (IAR != IAREnd
|
assert (IAR != IAREnd
|
||||||
&& "About to dereference past end of IncomingArgRegs");
|
&& "About to dereference past end of IncomingArgRegs");
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
|
||||||
BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
|
||||||
} else {
|
} else {
|
||||||
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||||
@ -418,19 +418,19 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
|||||||
unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
|
unsigned DblAlign = TM.getTargetData().getDoubleAlignment();
|
||||||
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
||||||
if (ArgOffset < 92 && IAR != IAREnd) {
|
if (ArgOffset < 92 && IAR != IAREnd) {
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (*IAR++);
|
||||||
} else {
|
} else {
|
||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
if (ArgOffset < 92 && IAR != IAREnd) {
|
if (ArgOffset < 92 && IAR != IAREnd) {
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (*IAR++);
|
||||||
} else {
|
} else {
|
||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDDFri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
|
||||||
@ -442,7 +442,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
|||||||
BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
|
BuildMI (BB, V8::ORrr, 2, ArgReg).addReg (V8::G0).addReg (*IAR++);
|
||||||
} else {
|
} else {
|
||||||
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||||
BuildMI (BB, V8::LD, 2, ArgReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, ArgReg).addFrameIndex (FI).addSImm (0);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
// ...then do the second half
|
// ...then do the second half
|
||||||
@ -452,7 +452,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
|||||||
BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
|
BuildMI (BB, V8::ORrr, 2, ArgReg+1).addReg (V8::G0).addReg (*IAR++);
|
||||||
} else {
|
} else {
|
||||||
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||||
BuildMI (BB, V8::LD, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, ArgReg+1).addFrameIndex (FI).addSImm (0);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
} else {
|
} else {
|
||||||
@ -644,7 +644,7 @@ void V8ISel::emitFPToIntegerCast (MachineBasicBlock *BB,
|
|||||||
BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
|
BuildMI (*BB, IP, FPStoreOpcode, 3).addFrameIndex (FI).addSImm (0)
|
||||||
.addReg (TempReg);
|
.addReg (TempReg);
|
||||||
unsigned TempReg2 = makeAnotherReg (newTy);
|
unsigned TempReg2 = makeAnotherReg (newTy);
|
||||||
BuildMI (*BB, IP, V8::LD, 3, TempReg2).addFrameIndex (FI).addSImm (0);
|
BuildMI (*BB, IP, V8::LDri, 3, TempReg2).addFrameIndex (FI).addSImm (0);
|
||||||
emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
|
emitIntegerCast (BB, IP, Type::IntTy, TempReg2, newTy, DestReg);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -698,7 +698,7 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
|
|||||||
// it using ldf into a floating point register. then do fitos.
|
// it using ldf into a floating point register. then do fitos.
|
||||||
unsigned TmpReg = makeAnotherReg (newTy);
|
unsigned TmpReg = makeAnotherReg (newTy);
|
||||||
int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
|
int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
|
||||||
BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
|
BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
|
||||||
.addReg (SrcReg);
|
.addReg (SrcReg);
|
||||||
BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
|
||||||
BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
|
BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
|
||||||
@ -720,7 +720,7 @@ void V8ISel::emitCastOperation(MachineBasicBlock *BB,
|
|||||||
unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
|
unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
|
||||||
unsigned TmpReg = makeAnotherReg (newTy);
|
unsigned TmpReg = makeAnotherReg (newTy);
|
||||||
int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
|
int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
|
||||||
BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
|
BuildMI (*BB, IP, V8::STri, 3).addFrameIndex (FI).addSImm (0)
|
||||||
.addReg (SrcReg);
|
.addReg (SrcReg);
|
||||||
BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
|
||||||
BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
|
BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
|
||||||
@ -774,22 +774,22 @@ void V8ISel::visitLoadInst(LoadInst &I) {
|
|||||||
switch (getClassB (I.getType ())) {
|
switch (getClassB (I.getType ())) {
|
||||||
case cByte:
|
case cByte:
|
||||||
if (I.getType ()->isSigned ())
|
if (I.getType ()->isSigned ())
|
||||||
BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDSBri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
else
|
else
|
||||||
BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDUBri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
return;
|
return;
|
||||||
case cShort:
|
case cShort:
|
||||||
if (I.getType ()->isSigned ())
|
if (I.getType ()->isSigned ())
|
||||||
BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDSHri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
else
|
else
|
||||||
BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDUHri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
return;
|
return;
|
||||||
case cInt:
|
case cInt:
|
||||||
BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
return;
|
return;
|
||||||
case cLong:
|
case cLong:
|
||||||
BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
|
BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (PtrReg).addSImm(4);
|
||||||
return;
|
return;
|
||||||
case cFloat:
|
case cFloat:
|
||||||
BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
|
||||||
@ -810,17 +810,17 @@ void V8ISel::visitStoreInst(StoreInst &I) {
|
|||||||
unsigned PtrReg = getReg (I.getOperand (1));
|
unsigned PtrReg = getReg (I.getOperand (1));
|
||||||
switch (getClassB (SrcVal->getType ())) {
|
switch (getClassB (SrcVal->getType ())) {
|
||||||
case cByte:
|
case cByte:
|
||||||
BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
BuildMI (BB, V8::STBri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
||||||
return;
|
return;
|
||||||
case cShort:
|
case cShort:
|
||||||
BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
BuildMI (BB, V8::STHri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
||||||
return;
|
return;
|
||||||
case cInt:
|
case cInt:
|
||||||
BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
||||||
return;
|
return;
|
||||||
case cLong:
|
case cLong:
|
||||||
BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
||||||
BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
|
BuildMI (BB, V8::STri, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
|
||||||
return;
|
return;
|
||||||
case cFloat:
|
case cFloat:
|
||||||
BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
|
||||||
@ -879,7 +879,7 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
|
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
|
||||||
} else {
|
} else {
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (ArgReg);
|
.addReg (ArgReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -892,7 +892,7 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
|
BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
|
||||||
assert (OAR != OAREnd &&
|
assert (OAR != OAREnd &&
|
||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
|
||||||
} else {
|
} else {
|
||||||
BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (ArgReg);
|
.addReg (ArgReg);
|
||||||
@ -909,22 +909,22 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
if (ArgOffset < 92 && OAR != OAREnd) {
|
if (ArgOffset < 92 && OAR != OAREnd) {
|
||||||
assert (OAR != OAREnd &&
|
assert (OAR != OAREnd &&
|
||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (0);
|
||||||
} else {
|
} else {
|
||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (0);
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (TempReg);
|
.addReg (TempReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
if (ArgOffset < 92 && OAR != OAREnd) {
|
if (ArgOffset < 92 && OAR != OAREnd) {
|
||||||
assert (OAR != OAREnd &&
|
assert (OAR != OAREnd &&
|
||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, *OAR++).addFrameIndex (FI).addSImm (4);
|
||||||
} else {
|
} else {
|
||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, TempReg).addFrameIndex (FI).addSImm (4);
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (TempReg);
|
.addReg (TempReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -935,7 +935,7 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
|
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
|
||||||
} else {
|
} else {
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (ArgReg);
|
.addReg (ArgReg);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -945,7 +945,7 @@ void V8ISel::visitCallInst(CallInst &I) {
|
|||||||
"About to dereference past end of OutgoingArgRegs");
|
"About to dereference past end of OutgoingArgRegs");
|
||||||
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
|
BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
|
||||||
} else {
|
} else {
|
||||||
BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
|
BuildMI (BB, V8::STri, 3).addReg (V8::SP).addSImm (ArgOffset)
|
||||||
.addReg (ArgReg+1);
|
.addReg (ArgReg+1);
|
||||||
}
|
}
|
||||||
ArgOffset += 4;
|
ArgOffset += 4;
|
||||||
@ -1756,7 +1756,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
|
|||||||
unsigned DestReg = getReg (CI.getOperand(1));
|
unsigned DestReg = getReg (CI.getOperand(1));
|
||||||
unsigned Tmp = makeAnotherReg(Type::IntTy);
|
unsigned Tmp = makeAnotherReg(Type::IntTy);
|
||||||
BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
|
BuildMI (BB, V8::ADDri, 2, Tmp).addReg (V8::FP).addSImm (VarArgsOffset);
|
||||||
BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
|
BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(Tmp);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -1767,7 +1767,7 @@ void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
|
|||||||
case Intrinsic::vacopy: {
|
case Intrinsic::vacopy: {
|
||||||
// Copy the va_list ptr (arg1) to the result.
|
// Copy the va_list ptr (arg1) to the result.
|
||||||
unsigned DestReg = getReg (CI.getOperand(1)), SrcReg = getReg (CI.getOperand (2));
|
unsigned DestReg = getReg (CI.getOperand(1)), SrcReg = getReg (CI.getOperand (2));
|
||||||
BuildMI(BB, V8::ST, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
|
BuildMI(BB, V8::STri, 3).addReg(DestReg).addSImm(0).addReg(SrcReg);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1778,21 +1778,21 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
|
|||||||
unsigned DestReg = getReg (I);
|
unsigned DestReg = getReg (I);
|
||||||
unsigned Size;
|
unsigned Size;
|
||||||
unsigned VAList = makeAnotherReg(Type::IntTy);
|
unsigned VAList = makeAnotherReg(Type::IntTy);
|
||||||
BuildMI(BB, V8::LD, 2, VAList).addReg(VAListPtr).addSImm(0);
|
BuildMI(BB, V8::LDri, 2, VAList).addReg(VAListPtr).addSImm(0);
|
||||||
|
|
||||||
switch (I.getType ()->getTypeID ()) {
|
switch (I.getType ()->getTypeID ()) {
|
||||||
case Type::PointerTyID:
|
case Type::PointerTyID:
|
||||||
case Type::UIntTyID:
|
case Type::UIntTyID:
|
||||||
case Type::IntTyID:
|
case Type::IntTyID:
|
||||||
Size = 4;
|
Size = 4;
|
||||||
BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, DestReg).addReg (VAList).addSImm (0);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case Type::ULongTyID:
|
case Type::ULongTyID:
|
||||||
case Type::LongTyID:
|
case Type::LongTyID:
|
||||||
Size = 8;
|
Size = 8;
|
||||||
BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, DestReg).addReg (VAList).addSImm (0);
|
||||||
BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, DestReg+1).addReg (VAList).addSImm (4);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case Type::DoubleTyID: {
|
case Type::DoubleTyID: {
|
||||||
@ -1801,10 +1801,10 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
|
|||||||
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
unsigned TempReg = makeAnotherReg (Type::IntTy);
|
||||||
unsigned TempReg2 = makeAnotherReg (Type::IntTy);
|
unsigned TempReg2 = makeAnotherReg (Type::IntTy);
|
||||||
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg).addReg (VAList).addSImm (0);
|
BuildMI (BB, V8::LDri, 2, TempReg).addReg (VAList).addSImm (0);
|
||||||
BuildMI (BB, V8::LD, 2, TempReg2).addReg (VAList).addSImm (4);
|
BuildMI (BB, V8::LDri, 2, TempReg2).addReg (VAList).addSImm (4);
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (0).addReg (TempReg);
|
||||||
BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
|
BuildMI (BB, V8::STri, 3).addFrameIndex (FI).addSImm (4).addReg (TempReg2);
|
||||||
BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
|
BuildMI (BB, V8::LDDFri, 2, DestReg).addFrameIndex (FI).addSImm (0);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -1817,6 +1817,6 @@ void V8ISel::visitVAArgInst (VAArgInst &I) {
|
|||||||
}
|
}
|
||||||
unsigned tmp = makeAnotherReg(Type::IntTy);
|
unsigned tmp = makeAnotherReg(Type::IntTy);
|
||||||
BuildMI (BB, V8::ADDri, 2, tmp).addReg(VAList).addSImm(Size);
|
BuildMI (BB, V8::ADDri, 2, tmp).addReg(VAList).addSImm(Size);
|
||||||
BuildMI(BB, V8::ST, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
|
BuildMI(BB, V8::STri, 3).addReg(VAListPtr).addSImm(0).addReg(VAList);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
@ -41,12 +41,10 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) {
|
|||||||
void SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned SrcReg, int FrameIdx,
|
unsigned SrcReg, int FrameIdx,
|
||||||
const TargetRegisterClass *rc) const {
|
const TargetRegisterClass *RC) const {
|
||||||
const TargetRegisterClass *RC = getClass(SrcReg);
|
|
||||||
|
|
||||||
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
|
// On the order of operands here: think "[FrameIdx + 0] = SrcReg".
|
||||||
if (RC == V8::IntRegsRegisterClass)
|
if (RC == V8::IntRegsRegisterClass)
|
||||||
BuildMI (MBB, I, V8::ST, 3).addFrameIndex (FrameIdx).addSImm (0)
|
BuildMI (MBB, I, V8::STri, 3).addFrameIndex (FrameIdx).addSImm (0)
|
||||||
.addReg (SrcReg);
|
.addReg (SrcReg);
|
||||||
else if (RC == V8::FPRegsRegisterClass)
|
else if (RC == V8::FPRegsRegisterClass)
|
||||||
BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
|
BuildMI (MBB, I, V8::STFri, 3).addFrameIndex (FrameIdx).addSImm (0)
|
||||||
@ -61,10 +59,9 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
|||||||
void SparcV8RegisterInfo::
|
void SparcV8RegisterInfo::
|
||||||
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||||
unsigned DestReg, int FrameIdx,
|
unsigned DestReg, int FrameIdx,
|
||||||
const TargetRegisterClass *rc) const {
|
const TargetRegisterClass *RC) const {
|
||||||
const TargetRegisterClass *RC = getClass(DestReg);
|
|
||||||
if (RC == V8::IntRegsRegisterClass)
|
if (RC == V8::IntRegsRegisterClass)
|
||||||
BuildMI (MBB, I, V8::LD, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
|
BuildMI (MBB, I, V8::LDri, 2, DestReg).addFrameIndex (FrameIdx).addSImm (0);
|
||||||
else if (RC == V8::FPRegsRegisterClass)
|
else if (RC == V8::FPRegsRegisterClass)
|
||||||
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
|
BuildMI (MBB, I, V8::LDFri, 2, DestReg).addFrameIndex (FrameIdx)
|
||||||
.addSImm (0);
|
.addSImm (0);
|
||||||
|
Loading…
Reference in New Issue
Block a user