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Emit more efficient 64-bit operations when the RHS is a constant, and one
of the words of the constant is zeros. For example: Y = and long X, 1234 now generates: Yl = and Xl, 1234 Yh = 0 instead of: Yl = and Xl, 1234 Yh = and Xh, 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12685 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1767,18 +1767,54 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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};
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
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uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v &0xFFFFFFFF);
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if (Class != cLong) {
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
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return;
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} else {
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// If this is a long value and the high or low bits have a special
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// property, emit some special cases.
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unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
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if (Class == cLong) {
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// If the constant is zero in the low 32-bits, just copy the low part
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// across and apply the normal 32-bit operation to the high parts. There
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// will be no carry or borrow into the top.
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if (Op1l == 0) {
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if (OperatorClass != 2) // All but and...
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
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else
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
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BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
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.addReg(Op0r+1).addImm(Op1h);
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return;
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}
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// If this is a logical operation and the top 32-bits are zero, just
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// operate on the lower 32.
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if (Op1h == 0 && OperatorClass > 1) {
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BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
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.addReg(Op0r).addImm(Op1l);
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if (OperatorClass != 2) // All but and
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
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else
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
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return;
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}
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// TODO: We could handle lots of other special cases here, such as AND'ing
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// with 0xFFFFFFFF00000000 -> noop, etc.
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// Otherwise, code generate the full operation with a constant.
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static const unsigned TopTab[] = {
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X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
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};
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
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BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
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.addReg(Op0r+1).addImm(uint64_t(Op1v) >> 32);
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.addReg(Op0r+1).addImm(Op1h);
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return;
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}
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return;
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}
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// Finally, handle the general case now.
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@ -1767,18 +1767,54 @@ void ISel::emitSimpleBinaryOperation(MachineBasicBlock *MBB,
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};
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unsigned Opcode = OpcodeTab[OperatorClass][Class];
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unsigned Op1l = cast<ConstantInt>(Op1C)->getRawValue();
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uint64_t Op1v = cast<ConstantInt>(Op1C)->getRawValue();
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1v &0xFFFFFFFF);
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if (Class != cLong) {
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
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return;
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} else {
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// If this is a long value and the high or low bits have a special
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// property, emit some special cases.
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unsigned Op1h = cast<ConstantInt>(Op1C)->getRawValue() >> 32LL;
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if (Class == cLong) {
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// If the constant is zero in the low 32-bits, just copy the low part
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// across and apply the normal 32-bit operation to the high parts. There
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// will be no carry or borrow into the top.
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if (Op1l == 0) {
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if (OperatorClass != 2) // All but and...
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg).addReg(Op0r);
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else
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg).addImm(0);
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BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg+1)
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.addReg(Op0r+1).addImm(Op1h);
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return;
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}
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// If this is a logical operation and the top 32-bits are zero, just
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// operate on the lower 32.
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if (Op1h == 0 && OperatorClass > 1) {
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BuildMI(*MBB, IP, OpcodeTab[OperatorClass][cLong], 2, DestReg)
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.addReg(Op0r).addImm(Op1l);
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if (OperatorClass != 2) // All but and
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BuildMI(*MBB, IP, X86::MOV32rr, 1, DestReg+1).addReg(Op0r+1);
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else
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BuildMI(*MBB, IP, X86::MOV32ri, 1, DestReg+1).addImm(0);
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return;
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}
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// TODO: We could handle lots of other special cases here, such as AND'ing
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// with 0xFFFFFFFF00000000 -> noop, etc.
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// Otherwise, code generate the full operation with a constant.
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static const unsigned TopTab[] = {
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X86::ADC32ri, X86::SBB32ri, X86::AND32ri, X86::OR32ri, X86::XOR32ri
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};
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BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addImm(Op1l);
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BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1)
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.addReg(Op0r+1).addImm(uint64_t(Op1v) >> 32);
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.addReg(Op0r+1).addImm(Op1h);
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return;
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}
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return;
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}
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// Finally, handle the general case now.
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