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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136367 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-07-28 17:56:55 +00:00
parent 8313b48bbe
commit 354712c5a5
1 changed files with 10 additions and 18 deletions
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28
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
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@ -921,17 +921,14 @@ unsigned ARMMCCodeEmitter::
getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
// shifted. The second is either Rs, the amount to shift by, or reg0 in which
// case the imm contains the amount to shift by.
// shifted. The second is Rs, the amount to shift by, and the third specifies
// the type of the shift.
//
// {3-0} = Rm.
// {4} = 1 if reg shift, 0 if imm shift
// {4} = 1
// {6-5} = type
// If reg shift:
// {11-8} = Rs
// {7} = 0
// else (imm shift)
// {11-7} = imm
// {11-8} = Rs
// {7} = 0
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
@ -961,7 +958,7 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
Binary |= SBits << 4;
// Encode the shift operation Rs or shift_imm (except rrx).
// Encode the shift operation Rs.
// Encode Rs bit[11:8].
assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
@ -970,18 +967,13 @@ getSORegRegOpValue(const MCInst &MI, unsigned OpIdx,
unsigned ARMMCCodeEmitter::
getSORegImmOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const {
// Sub-operands are [reg, reg, imm]. The first register is Rm, the reg to be
// shifted. The second is either Rs, the amount to shift by, or reg0 in which
// case the imm contains the amount to shift by.
// Sub-operands are [reg, imm]. The first register is Rm, the reg to be
// shifted. The second is the amount to shift by.
//
// {3-0} = Rm.
// {4} = 1 if reg shift, 0 if imm shift
// {4} = 0
// {6-5} = type
// If reg shift:
// {11-8} = Rs
// {7} = 0
// else (imm shift)
// {11-7} = imm
// {11-7} = imm
const MCOperand &MO = MI.getOperand(OpIdx);
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);