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https://github.com/c64scene-ar/llvm-6502.git
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Two-address instructions no longer have to be A := A op C. Now any pair of dest / src operands can be tied together.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31363 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
e0805a2d36
commit
360c2dd25a
@ -199,17 +199,20 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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unsigned physReg = Virt2PhysRegMap[virtualReg];
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if (physReg == 0) {
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if (op.isDef()) {
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if (!TM->getInstrInfo()->isTwoAddrInstr(MI->getOpcode()) || i) {
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int TiedOp = TM->getInstrInfo()
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->getTiedToSrcOperand(MI->getOpcode(), i);
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if (TiedOp == -1) {
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physReg = getFreeReg(virtualReg);
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} else {
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// must be same register number as the first operand
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// This maps a = b + c into b = b + c, and saves b into a's spot.
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assert(MI->getOperand(1).isRegister() &&
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MI->getOperand(1).getReg() &&
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MI->getOperand(1).isUse() &&
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// must be same register number as the source operand that is
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// tied to. This maps a = b + c into b = b + c, and saves b into
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// a's spot.
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assert(MI->getOperand(TiedOp).isRegister() &&
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MI->getOperand(TiedOp).getReg() &&
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MI->getOperand(TiedOp).isUse() &&
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"Two address instruction invalid!");
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physReg = MI->getOperand(1).getReg();
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physReg = MI->getOperand(TiedOp).getReg();
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}
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spillVirtReg(MBB, next(MI), virtualReg, physReg);
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} else {
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@ -95,122 +95,141 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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mi != me; ++mi) {
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unsigned opcode = mi->getOpcode();
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// ignore if it is not a two-address instruction
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if (!TII.isTwoAddrInstr(opcode))
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continue;
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bool FirstTied = true;
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for (unsigned si = 1, e = TII.getNumOperands(opcode); si < e; ++si) {
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int ti = TII.getOperandConstraint(opcode, si, TargetInstrInfo::TIED_TO);
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if (ti == -1)
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continue;
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++NumTwoAddressInstrs;
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
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assert(mi->getOperand(1).isRegister() && mi->getOperand(1).getReg() &&
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mi->getOperand(1).isUse() && "two address instruction invalid");
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if (FirstTied) {
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++NumTwoAddressInstrs;
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
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}
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FirstTied = false;
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// if the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(0).getReg() != mi->getOperand(1).getReg()) {
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(0).getReg();
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unsigned regB = mi->getOperand(1).getReg();
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assert(mi->getOperand(si).isRegister() && mi->getOperand(si).getReg() &&
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mi->getOperand(si).isUse() && "two address instruction invalid");
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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// if the two operands are the same we just remove the use
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// and mark the def as def&use, otherwise we have to insert a copy.
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if (mi->getOperand(ti).getReg() != mi->getOperand(si).getReg()) {
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// rewrite:
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// a = b op c
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// to:
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// a = b
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// a = a op c
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unsigned regA = mi->getOperand(ti).getReg();
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unsigned regB = mi->getOperand(si).getReg();
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assert(MRegisterInfo::isVirtualRegister(regA) &&
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MRegisterInfo::isVirtualRegister(regB) &&
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"cannot update physical register live information");
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#ifndef NDEBUG
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// First, verify that we do not have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 1; i != mi->getNumOperands(); ++i)
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assert(!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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// First, verify that we don't have a use of a in the instruction (a =
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// b + a for example) because our transformation will not work. This
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// should never occur because we are in SSA form.
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for (unsigned i = 0; i != mi->getNumOperands(); ++i)
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assert((int)i == ti ||
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!mi->getOperand(i).isRegister() ||
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mi->getOperand(i).getReg() != regA);
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#endif
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!LV.KillsRegister(mi, regB)) {
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const TargetInstrDescriptor &TID = TII.get(opcode);
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// If this instruction is not the killing user of B, see if we can
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// rearrange the code to make it so. Making it the killing user will
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// allow us to coalesce A and B together, eliminating the copy we are
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// about to insert.
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if (!LV.KillsRegister(mi, regB)) {
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const TargetInstrDescriptor &TID = TII.get(opcode);
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// If this instruction is commutative, check to see if C dies. If so,
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// swap the B and C operands. This makes the live ranges of A and C
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// joinable.
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if (TID.Flags & M_COMMUTABLE) {
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assert(mi->getOperand(2).isRegister() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(2).getReg();
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if (LV.KillsRegister(mi, regC)) {
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DEBUG(std::cerr << "2addr: COMMUTING : " << *mi);
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MachineInstr *NewMI = TII.commuteInstruction(mi);
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if (NewMI == 0) {
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DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
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} else {
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DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
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// If the instruction changed to commute it, update livevar.
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if (NewMI != mi) {
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LV.instructionChanged(mi, NewMI); // Update live variables
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mbbi->insert(mi, NewMI); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = NewMI;
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// If this instruction is commutative, check to see if C dies. If
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// so, swap the B and C operands. This makes the live ranges of A
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// and C joinable.
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// FIXME: This code also works for A := B op C instructions.
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if ((TID.Flags & M_COMMUTABLE) && mi->getNumOperands() == 3) {
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assert(mi->getOperand(3-si).isRegister() &&
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"Not a proper commutative instruction!");
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unsigned regC = mi->getOperand(3-si).getReg();
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if (LV.KillsRegister(mi, regC)) {
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DEBUG(std::cerr << "2addr: COMMUTING : " << *mi);
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MachineInstr *NewMI = TII.commuteInstruction(mi);
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if (NewMI == 0) {
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DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
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} else {
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DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
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// If the instruction changed to commute it, update livevar.
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if (NewMI != mi) {
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LV.instructionChanged(mi, NewMI); // Update live variables
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mbbi->insert(mi, NewMI); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = NewMI;
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}
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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++NumCommuted;
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regB = regC;
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goto InstructionRearranged;
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}
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}
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
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// FIXME: This assumes there are no more operands which are tied
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// to another register.
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#ifndef NDEBUG
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for (unsigned i = si+1, e = TII.getNumOperands(opcode); i < e; ++i)
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assert(TII.getOperandConstraint(opcode, i,
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TargetInstrInfo::TIED_TO) == -1);
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#endif
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if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
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DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
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DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New);
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LV.instructionChanged(mi, New); // Update live variables
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mbbi->insert(mi, New); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = New;
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++NumConvertedTo3Addr;
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assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
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"convertToThreeAddress returned a 2-addr instruction??");
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// Done with this instruction.
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break;
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
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MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
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MachineBasicBlock::iterator prevMi = prior(mi);
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DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
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// Update live variables for regA
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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varInfo.DefInst = prevMi;
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// update live variables for regB
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if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
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LV.addVirtualRegisterKilled(regB, prevMi);
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if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
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LV.addVirtualRegisterDead(regB, prevMi);
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// replace all occurences of regB with regA
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for (unsigned i = 0, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->getOperand(i).setReg(regA);
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}
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// If this instruction is potentially convertible to a true
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// three-address instruction,
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if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
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if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
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DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
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DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New);
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LV.instructionChanged(mi, New); // Update live variables
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mbbi->insert(mi, New); // Insert the new inst
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mbbi->erase(mi); // Nuke the old inst.
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mi = New;
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++NumConvertedTo3Addr;
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assert(!TII.isTwoAddrInstr(New->getOpcode()) &&
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"convertToThreeAddress returned a 2-addr instruction??");
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// Done with this instruction.
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continue;
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}
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}
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InstructionRearranged:
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const TargetRegisterClass* rc = MF.getSSARegMap()->getRegClass(regA);
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MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
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MachineBasicBlock::iterator prevMi = prior(mi);
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DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
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assert(mi->getOperand(ti).isDef() && mi->getOperand(si).isUse());
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mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
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MadeChange = true;
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// Update live variables for regA
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LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
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varInfo.DefInst = prevMi;
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// update live variables for regB
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if (LV.removeVirtualRegisterKilled(regB, mbbi, mi))
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LV.addVirtualRegisterKilled(regB, prevMi);
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if (LV.removeVirtualRegisterDead(regB, mbbi, mi))
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LV.addVirtualRegisterDead(regB, prevMi);
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// replace all occurences of regB with regA
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for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->getOperand(i).setReg(regA);
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}
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DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
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}
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assert(mi->getOperand(0).isDef() && mi->getOperand(1).isUse());
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mi->getOperand(1).setReg(mi->getOperand(0).getReg());
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MadeChange = true;
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DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
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}
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}
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@ -98,7 +98,8 @@ void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
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}
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ModRef MRInfo;
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if (OpNo < 2 && TII.isTwoAddrInstr(OldMI->getOpcode())) {
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if (TII.getOperandConstraint(OldMI->getOpcode(), OpNo,
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TargetInstrInfo::TIED_TO)) {
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// Folded a two-address operand.
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MRInfo = isModRef;
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} else if (OldMI->getOperand(OpNo).isDef()) {
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@ -560,9 +561,11 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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// aren't allowed to modify the reused register. If none of these cases
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// apply, reuse it.
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bool CanReuse = true;
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if (i == 1 && MI.getOperand(0).isReg() &&
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MI.getOperand(0).getReg() == VirtReg &&
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TII->isTwoAddrInstr(MI.getOpcode())) {
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int ti = TII->getOperandConstraint(MI.getOpcode(), i,
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TargetInstrInfo::TIED_TO);
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if (ti != -1 &&
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MI.getOperand(ti).isReg() &&
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MI.getOperand(ti).getReg() == VirtReg) {
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// Okay, we have a two address operand. We can reuse this physreg as
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// long as we are allowed to clobber the value.
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CanReuse = Spills.canClobberPhysReg(StackSlot);
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@ -818,8 +821,9 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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// If this def is part of a two-address operand, make sure to execute
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// the store from the correct physical register.
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unsigned PhysReg;
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if (i == 0 && TII->isTwoAddrInstr(MI.getOpcode()))
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PhysReg = MI.getOperand(1).getReg();
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int TiedOp = TII->getTiedToSrcOperand(MI.getOpcode(), i);
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if (TiedOp != -1)
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PhysReg = MI.getOperand(TiedOp).getReg();
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else
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PhysReg = VRM.getPhys(VirtReg);
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