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ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2
Re-apply r241926 with an additional check that r13 and r15 are not used for LDRD/STRD. See http://llvm.org/PR24190. This also already includes the fix from r241951. Differential Revision: http://reviews.llvm.org/D10623 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242742 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -111,8 +111,12 @@ namespace {
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/// Index into the basic block where the merged instruction will be
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/// inserted. (See MemOpQueueEntry.Position)
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unsigned InsertPos;
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/// Whether the instructions can be merged into a ldm/stm instruction.
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bool CanMergeToLSMulti;
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/// Whether the instructions can be merged into a ldrd/strd instruction.
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bool CanMergeToLSDouble;
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};
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BumpPtrAllocator Allocator;
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SpecificBumpPtrAllocator<MergeCandidate> Allocator;
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SmallVector<const MergeCandidate*,4> Candidates;
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void moveLiveRegsBefore(const MachineBasicBlock &MBB,
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@ -122,11 +126,14 @@ namespace {
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MachineBasicBlock::iterator MBBI,
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DebugLoc DL, unsigned Base, unsigned WordOffset,
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ARMCC::CondCodes Pred, unsigned PredReg);
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MachineInstr *MergeOps(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore, int Offset,
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unsigned Base, bool BaseKill, unsigned Opcode,
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ARMCC::CondCodes Pred, unsigned PredReg, DebugLoc DL,
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ArrayRef<std::pair<unsigned, bool>> Regs);
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MachineInstr *CreateLoadStoreMulti(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base,
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bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
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DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs);
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MachineInstr *CreateLoadStoreDouble(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base,
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bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
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DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const;
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void FormCandidates(const MemOpQueue &MemOps);
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MachineInstr *MergeOpsUpdate(const MergeCandidate &Cand);
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bool FixInvalidRegPairOp(MachineBasicBlock &MBB,
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@ -555,12 +562,10 @@ static bool ContainsReg(const ArrayRef<std::pair<unsigned, bool>> &Regs,
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/// Create and insert a LDM or STM with Base as base register and registers in
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/// Regs as the register operands that would be loaded / stored. It returns
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/// true if the transformation is done.
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MachineInstr *
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ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore, int Offset,
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unsigned Base, bool BaseKill, unsigned Opcode,
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ARMCC::CondCodes Pred, unsigned PredReg, DebugLoc DL,
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ArrayRef<std::pair<unsigned, bool>> Regs) {
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MachineInstr *ARMLoadStoreOpt::CreateLoadStoreMulti(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base,
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bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
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DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) {
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unsigned NumRegs = Regs.size();
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assert(NumRegs > 1);
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@ -749,6 +754,28 @@ ARMLoadStoreOpt::MergeOps(MachineBasicBlock &MBB,
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return MIB.getInstr();
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}
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MachineInstr *ARMLoadStoreOpt::CreateLoadStoreDouble(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator InsertBefore, int Offset, unsigned Base,
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bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg,
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DebugLoc DL, ArrayRef<std::pair<unsigned, bool>> Regs) const {
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bool IsLoad = isi32Load(Opcode);
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assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store");
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unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8;
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assert(Regs.size() == 2);
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MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
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TII->get(LoadStoreOpcode));
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if (IsLoad) {
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MIB.addReg(Regs[0].first, RegState::Define)
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.addReg(Regs[1].first, RegState::Define);
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} else {
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MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
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.addReg(Regs[1].first, getKillRegState(Regs[1].second));
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}
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MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
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return MIB.getInstr();
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}
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/// Call MergeOps and update MemOps and merges accordingly on success.
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MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
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const MachineInstr *First = Cand.Instrs.front();
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@ -799,7 +826,12 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
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unsigned PredReg = 0;
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ARMCC::CondCodes Pred = getInstrPredicate(First, PredReg);
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DebugLoc DL = First->getDebugLoc();
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MachineInstr *Merged = MergeOps(MBB, InsertBefore, Offset, Base, BaseKill,
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MachineInstr *Merged = nullptr;
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if (Cand.CanMergeToLSDouble)
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Merged = CreateLoadStoreDouble(MBB, InsertBefore, Offset, Base, BaseKill,
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Opcode, Pred, PredReg, DL, Regs);
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if (!Merged && Cand.CanMergeToLSMulti)
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Merged = CreateLoadStoreMulti(MBB, InsertBefore, Offset, Base, BaseKill,
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Opcode, Pred, PredReg, DL, Regs);
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if (!Merged)
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return nullptr;
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@ -861,6 +893,13 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) {
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return Merged;
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}
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static bool isValidLSDoubleOffset(int Offset) {
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unsigned Value = abs(Offset);
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// t2LDRDi8/t2STRDi8 supports an 8 bit immediate which is internally
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// multiplied by 4.
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return (Value % 4) == 0 && Value < 1024;
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}
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/// Find candidates for load/store multiple merge in list of MemOpQueueEntries.
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void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
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const MachineInstr *FirstMI = MemOps[0].MI;
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@ -880,29 +919,55 @@ void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
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unsigned Latest = SIndex;
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unsigned Earliest = SIndex;
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unsigned Count = 1;
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bool CanMergeToLSDouble =
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STI->isThumb2() && isNotVFP && isValidLSDoubleOffset(Offset);
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// ARM errata 602117: LDRD with base in list may result in incorrect base
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// register when interrupted or faulted.
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if (STI->isCortexM3() && isi32Load(Opcode) &&
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PReg == getLoadStoreBaseOp(*MI).getReg())
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CanMergeToLSDouble = false;
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// Merge additional instructions fulfilling LDM/STM constraints.
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bool CanMergeToLSMulti = true;
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// On swift vldm/vstm starting with an odd register number as that needs
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// more uops than single vldrs.
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if (STI->isSwift() && !isNotVFP && (PRegNum % 2) == 1)
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CanMergeToLSMulti = false;
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// LDRD/STRD do not allow SP/PC. LDM/STM do not support it or have it
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// deprecated; LDM to PC is fine but cannot happen here.
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if (PReg == ARM::SP || PReg == ARM::PC)
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CanMergeToLSMulti = CanMergeToLSDouble = false;
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// Merge following instructions where possible.
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for (unsigned I = SIndex+1; I < EIndex; ++I, ++Count) {
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int NewOffset = MemOps[I].Offset;
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if (NewOffset != Offset + (int)Size)
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break;
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const MachineOperand &MO = getLoadStoreRegOp(*MemOps[I].MI);
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unsigned Reg = MO.getReg();
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if (Reg == ARM::SP)
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break;
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unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
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// Register numbers must be in ascending order.
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if (RegNum <= PRegNum)
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break;
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// For VFP / NEON load/store multiples, the registers must be consecutive
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// and within the limit on the number of registers per instruction.
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if (!isNotVFP && RegNum != PRegNum+1)
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break;
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// On Swift we don't want vldm/vstm to start with a odd register num
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// because Q register unaligned vldm/vstm need more uops.
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if (!isNotVFP && STI->isSwift() && Count == 1 && (PRegNum % 2) == 1)
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if (Reg == ARM::SP || Reg == ARM::PC)
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break;
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// See if the current load/store may be part of a multi load/store.
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unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
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bool PartOfLSMulti = CanMergeToLSMulti;
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if (PartOfLSMulti) {
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// Register numbers must be in ascending order.
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if (RegNum <= PRegNum)
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PartOfLSMulti = false;
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// For VFP / NEON load/store multiples, the registers must be
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// consecutive and within the limit on the number of registers per
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// instruction.
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else if (!isNotVFP && RegNum != PRegNum+1)
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PartOfLSMulti = false;
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}
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// See if the current load/store may be part of a double load/store.
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bool PartOfLSDouble = CanMergeToLSDouble && Count <= 1;
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if (!PartOfLSMulti && !PartOfLSDouble)
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break;
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CanMergeToLSMulti &= PartOfLSMulti;
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CanMergeToLSDouble &= PartOfLSDouble;
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// Track MemOp with latest and earliest position (Positions are
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// counted in reverse).
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unsigned Position = MemOps[I].Position;
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@ -916,12 +981,16 @@ void ARMLoadStoreOpt::FormCandidates(const MemOpQueue &MemOps) {
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}
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// Form a candidate from the Ops collected so far.
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MergeCandidate *Candidate = new(Allocator) MergeCandidate;
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MergeCandidate *Candidate = new(Allocator.Allocate()) MergeCandidate;
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for (unsigned C = SIndex, CE = SIndex + Count; C < CE; ++C)
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Candidate->Instrs.push_back(MemOps[C].MI);
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Candidate->LatestMIIdx = Latest - SIndex;
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Candidate->EarliestMIIdx = Earliest - SIndex;
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Candidate->InsertPos = MemOps[Latest].Position;
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if (Count == 1)
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CanMergeToLSMulti = CanMergeToLSDouble = false;
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Candidate->CanMergeToLSMulti = CanMergeToLSMulti;
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Candidate->CanMergeToLSDouble = CanMergeToLSDouble;
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Candidates.push_back(Candidate);
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// Continue after the chain.
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SIndex += Count;
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@ -1653,12 +1722,14 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// Go through list of candidates and merge.
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bool Changed = false;
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for (const MergeCandidate *Candidate : Candidates) {
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if (Candidate->Instrs.size() > 1) {
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if (Candidate->CanMergeToLSMulti || Candidate->CanMergeToLSDouble) {
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MachineInstr *Merged = MergeOpsUpdate(*Candidate);
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// Merge preceding/trailing base inc/dec into the merged op.
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if (Merged) {
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MergeBaseUpdateLSMultiple(Merged);
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Changed = true;
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unsigned Opcode = Merged->getOpcode();
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if (Opcode != ARM::t2STRDi8 && Opcode != ARM::t2LDRDi8)
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MergeBaseUpdateLSMultiple(Merged);
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} else {
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for (MachineInstr *MI : Candidate->Instrs) {
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if (MergeBaseUpdateLoadStore(MI))
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@ -1738,7 +1809,7 @@ bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
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Modified |= MergeReturnIntoLDM(MBB);
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}
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Allocator.Reset();
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Allocator.DestroyAll();
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return Modified;
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}
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@ -25,8 +25,7 @@ entry:
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;CHECK: push {r7, lr}
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;CHECK: sub sp, #4
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;CHECK: add r0, sp, #12
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;CHECK: str r2, [sp, #16]
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;CHECK: str r1, [sp, #12]
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;CHECK: strd r1, r2, [sp, #12]
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;CHECK: bl fooUseStruct
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call void @fooUseStruct(%st_t* %p1)
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ret void
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@ -28,8 +28,7 @@ define i32 @test_align8(i8*, [4 x i32]* byval align 8 %b) {
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; CHECK: push {r4, r7, lr}
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; CHECK: add r7, sp, #4
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; CHECK-DAG: str r2, [r7, #8]
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; CHECK-DAG: str r3, [r7, #12]
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; CHECK: strd r2, r3, [r7, #8]
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; CHECK: ldr r0, [r7, #8]
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@ -3,6 +3,7 @@
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; rdar://6949835
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK
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; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT -check-prefix=CHECK
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; Magic ARM pair hints works best with linearscan / fast.
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@ -110,5 +111,25 @@ entry:
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ret void
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}
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; CHECK-LABEL: strd_spill_ldrd_reload:
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; A8: strd r1, r0, [sp]
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; M3: strd r1, r0, [sp]
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; BASIC: strd r1, r0, [sp]
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; GREEDY: strd r0, r1, [sp]
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; CHECK: @ InlineAsm Start
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; CHECK: @ InlineAsm End
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; A8: ldrd r2, r1, [sp]
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; M3: ldrd r2, r1, [sp]
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; BASIC: ldrd r2, r1, [sp]
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; GREEDY: ldrd r1, r2, [sp]
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; CHECK: bl{{x?}} _extfunc
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define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) {
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; force %v0 and %v1 to be spilled
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call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{lr}"()
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; force the reloaded %v0, %v1 into different registers
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call void @extfunc(i32 0, i32 %v0, i32 %v1, i32 7)
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ret void
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}
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declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
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declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind
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@ -4,8 +4,7 @@ define void @t1(i8* nocapture %c) nounwind optsize {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: movs r1, #0
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; CHECK: str r1, [r0]
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; CHECK: str r1, [r0, #4]
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; CHECK: strd r1, r1, [r0]
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; CHECK: str r1, [r0, #8]
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call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
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ret void
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@ -5,16 +5,20 @@ target triple = "thumbv7--linux-gnueabi"
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declare i8* @llvm.returnaddress(i32)
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define i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0) minsize {
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define i32* @wrong-t2stmia-size-reduction(i32* %addr, i32 %val0, i32 %val1) minsize {
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store i32 %val0, i32* %addr
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%addr1 = getelementptr i32, i32* %addr, i32 1
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%addr2 = getelementptr i32, i32* %addr, i32 2
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%lr = call i8* @llvm.returnaddress(i32 0)
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%lr32 = ptrtoint i8* %lr to i32
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store i32 %lr32, i32* %addr1
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%addr2 = getelementptr i32, i32* %addr1, i32 1
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ret i32* %addr2
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store i32 %val1, i32* %addr1
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store i32 %lr32, i32* %addr2
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%addr3 = getelementptr i32, i32* %addr, i32 3
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ret i32* %addr3
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}
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; Check that stm writes two registers. The bug caused one of registers (LR,
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; Check that stm writes three registers. The bug caused one of registers (LR,
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; which invalid for Thumb1 form of STMIA instruction) to be dropped.
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; CHECK: stm{{[^,]*}}, {{{.*,.*}}}
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; CHECK-LABEL: wrong-t2stmia-size-reduction:
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; CHECK: stm{{[^,]*}}, {{{.*,.*,.*}}}
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@ -33,8 +33,7 @@ define float @float_on_stack(double %a, double %b, double %c, double %d, double
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define double @double_on_stack(double %a, double %b, double %c, double %d, double %e, double %f, double %g, double %h, double %i) {
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; CHECK-LABEL: double_on_stack:
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; SOFT: ldr r0, [sp, #48]
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; SOFT: ldr r1, [sp, #52]
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; SOFT: ldrd r0, r1, [sp, #48]
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; HARD: vldr d0, [sp]
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; CHECK-NEXT: bx lr
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ret double %i
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@ -42,8 +41,7 @@ define double @double_on_stack(double %a, double %b, double %c, double %d, doubl
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define double @double_not_split(double %a, double %b, double %c, double %d, double %e, double %f, double %g, float %h, double %i) {
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; CHECK-LABEL: double_not_split:
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; SOFT: ldr r0, [sp, #48]
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; SOFT: ldr r1, [sp, #52]
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; SOFT: ldrd r0, r1, [sp, #48]
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; HARD: vldr d0, [sp]
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; CHECK-NEXT: bx lr
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ret double %i
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