mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-15 07:34:33 +00:00
Refactor code. No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60478 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
0ea25cb941
commit
370e5340a5
@ -5130,6 +5130,11 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
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return Result;
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}
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// isX86LogicalCmp - Return true if opcode is a X86 logical comparison.
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static bool isX86LogicalCmp(unsigned Opc) {
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return Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI;
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}
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SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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bool addTest = true;
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SDValue Cond = Op.getOperand(0);
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@ -5152,9 +5157,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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!isScalarFPTypeInSSEReg(VT)) // FPStack?
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IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
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if ((Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) && !IllegalFPCMov) {
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if (isX86LogicalCmp(Opc) && !IllegalFPCMov) {
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Cond = Cmp;
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addTest = false;
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}
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@ -5177,6 +5180,19 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::CMOV, VTs, 2, &Ops[0], Ops.size());
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}
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// isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
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// ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
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// from the AND / OR.
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static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) {
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Opc = Op.getOpcode();
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if (Opc != ISD::OR && Opc != ISD::AND)
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return false;
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return (Op.getOperand(0).getOpcode() == X86ISD::SETCC &&
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Op.getOperand(0).hasOneUse() &&
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Op.getOperand(1).getOpcode() == X86ISD::SETCC &&
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Op.getOperand(1).hasOneUse());
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}
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SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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bool addTest = true;
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SDValue Chain = Op.getOperand(0);
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@ -5196,86 +5212,73 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) {
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SDValue Cmp = Cond.getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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if (Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) {
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if (isX86LogicalCmp(Opc)) {
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Cond = Cmp;
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addTest = false;
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} else {
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ConstantSDNode *CSDN = cast<ConstantSDNode>(CC.getNode());
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switch (CSDN->getZExtValue()) {
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switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
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default: break;
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case X86::COND_O:
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case X86::COND_C:
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// These can only come from an arithmetic instruction with overflow, e.g.
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// SADDO, UADDO.
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Cond = Cond.getNode()->getOperand(1);
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addTest = false;
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break;
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}
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}
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// Also, recognize the pattern generated by an FCMP_UNE. We can emit
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// two branches instead of an explicit OR instruction with a
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// separate test.
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} else if (Cond.getOpcode() == ISD::OR &&
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Cond.hasOneUse() &&
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC &&
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Cond.getOperand(0).hasOneUse() &&
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Cond.getOperand(1).getOpcode() == X86ISD::SETCC &&
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Cond.getOperand(1).hasOneUse()) {
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SDValue Cmp = Cond.getOperand(0).getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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if (Cmp == Cond.getOperand(1).getOperand(1) &&
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(Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI)) {
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CC = Cond.getOperand(0).getOperand(0);
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Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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CC = Cond.getOperand(1).getOperand(0);
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Cond = Cmp;
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addTest = false;
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}
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// Also, recognize the pattern generated by an FCMP_OEQ. We can emit
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// two branches instead of an explicit AND instruction with a
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// separate test. However, we only do this if this block doesn't
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// have a fall-through edge, because this requires an explicit
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// jmp when the condition is false.
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} else if (Cond.getOpcode() == ISD::AND &&
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Cond.hasOneUse() &&
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Cond.getOperand(0).getOpcode() == X86ISD::SETCC &&
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Cond.getOperand(0).hasOneUse() &&
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Cond.getOperand(1).getOpcode() == X86ISD::SETCC &&
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Cond.getOperand(1).hasOneUse()) {
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SDValue Cmp = Cond.getOperand(0).getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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if (Cmp == Cond.getOperand(1).getOperand(1) &&
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(Opc == X86ISD::CMP ||
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Opc == X86ISD::COMI ||
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Opc == X86ISD::UCOMI) &&
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Op.getNode()->hasOneUse()) {
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X86::CondCode CCode =
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(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
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CCode = X86::GetOppositeBranchCondition(CCode);
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CC = DAG.getConstant(CCode, MVT::i8);
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SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
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// Look for an unconditional branch following this conditional branch.
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// We need this because we need to reverse the successors in order
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// to implement FCMP_OEQ.
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if (User.getOpcode() == ISD::BR) {
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SDValue FalseBB = User.getOperand(1);
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SDValue NewBR =
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DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
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assert(NewBR == User);
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Dest = FalseBB;
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} else {
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unsigned CondOpc;
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if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) {
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SDValue Cmp = Cond.getOperand(0).getOperand(1);
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unsigned Opc = Cmp.getOpcode();
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if (CondOpc == ISD::OR) {
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// Also, recognize the pattern generated by an FCMP_UNE. We can emit
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// two branches instead of an explicit OR instruction with a
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// separate test.
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if (Cmp == Cond.getOperand(1).getOperand(1) &&
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isX86LogicalCmp(Opc)) {
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CC = Cond.getOperand(0).getOperand(0);
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Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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CC = Cond.getOperand(1).getOperand(0);
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Cond = Cmp;
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addTest = false;
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}
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} else { // ISD::AND
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// Also, recognize the pattern generated by an FCMP_OEQ. We can emit
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// two branches instead of an explicit AND instruction with a
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// separate test. However, we only do this if this block doesn't
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// have a fall-through edge, because this requires an explicit
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// jmp when the condition is false.
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if (Cmp == Cond.getOperand(1).getOperand(1) &&
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isX86LogicalCmp(Opc) &&
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Op.getNode()->hasOneUse()) {
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X86::CondCode CCode =
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(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);
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CCode = X86::GetOppositeBranchCondition(CCode);
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CC = DAG.getConstant(CCode, MVT::i8);
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SDValue User = SDValue(*Op.getNode()->use_begin(), 0);
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// Look for an unconditional branch following this conditional branch.
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// We need this because we need to reverse the successors in order
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// to implement FCMP_OEQ.
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if (User.getOpcode() == ISD::BR) {
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SDValue FalseBB = User.getOperand(1);
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SDValue NewBR =
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DAG.UpdateNodeOperands(User, User.getOperand(0), Dest);
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assert(NewBR == User);
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Dest = FalseBB;
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Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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X86::CondCode CCode =
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(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
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CCode = X86::GetOppositeBranchCondition(CCode);
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CC = DAG.getConstant(CCode, MVT::i8);
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Cond = Cmp;
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addTest = false;
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Chain = DAG.getNode(X86ISD::BRCOND, Op.getValueType(),
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Chain, Dest, CC, Cmp);
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X86::CondCode CCode =
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(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);
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CCode = X86::GetOppositeBranchCondition(CCode);
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CC = DAG.getConstant(CCode, MVT::i8);
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Cond = Cmp;
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addTest = false;
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}
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}
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}
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}
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}
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