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https://github.com/c64scene-ar/llvm-6502.git
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Replace unpckl_undef and unpckh_undef matching with target specific opcodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112806 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2601,7 +2601,14 @@ static bool isTargetShuffle(unsigned Opcode) {
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case X86ISD::MOVSLDUP:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLPS:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHDQ:
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return true;
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}
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return false;
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@ -2655,7 +2662,14 @@ static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT,
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case X86ISD::MOVLPD:
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case X86ISD::MOVSS:
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case X86ISD::MOVSD:
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case X86ISD::UNPCKLPS:
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case X86ISD::PUNPCKLWD:
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case X86ISD::PUNPCKLBW:
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case X86ISD::PUNPCKLDQ:
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case X86ISD::UNPCKHPS:
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case X86ISD::PUNPCKHWD:
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case X86ISD::PUNPCKHBW:
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case X86ISD::PUNPCKHDQ:
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return DAG.getNode(Opc, dl, VT, V1, V2);
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}
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return SDValue();
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@ -5181,11 +5195,32 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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}
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}
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if (OptForSize) { // NOTE: isPSHUFDMask can also match this mask...
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if (HasSSE2 && X86::isUNPCKL_v_undef_Mask(SVOp) && VT == MVT::v4i32)
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if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) {
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// NOTE: isPSHUFDMask can also match this mask, if speed is more
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// important than size here, this will be matched by pshufd
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if (VT == MVT::v4f32)
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return getTargetShuffleNode(X86ISD::UNPCKLPS, dl, VT, V1, V1, DAG);
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if (HasSSE2 && VT == MVT::v16i8)
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return getTargetShuffleNode(X86ISD::PUNPCKLBW, dl, VT, V1, V1, DAG);
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if (HasSSE2 && VT == MVT::v8i16)
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return getTargetShuffleNode(X86ISD::PUNPCKLWD, dl, VT, V1, V1, DAG);
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if (HasSSE2 && VT == MVT::v4i32)
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return getTargetShuffleNode(X86ISD::PUNPCKLDQ, dl, VT, V1, V1, DAG);
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}
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if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) {
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// NOTE: isPSHUFDMask can also match this mask, if speed is more
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// important than size here, this will be matched by pshufd
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if (VT == MVT::v4f32)
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return getTargetShuffleNode(X86ISD::UNPCKHPS, dl, VT, V1, V1, DAG);
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if (HasSSE2 && VT == MVT::v16i8)
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return getTargetShuffleNode(X86ISD::PUNPCKHBW, dl, VT, V1, V1, DAG);
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if (HasSSE2 && VT == MVT::v8i16)
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return getTargetShuffleNode(X86ISD::PUNPCKHWD, dl, VT, V1, V1, DAG);
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if (HasSSE2 && VT == MVT::v4i32)
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return getTargetShuffleNode(X86ISD::PUNPCKHDQ, dl, VT, V1, V1, DAG);
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}
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if (X86::isPSHUFDMask(SVOp)) {
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// The actual implementation will match the mask in the if above and then
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// during isel it can match several different instructions, not only pshufd
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@ -5291,8 +5326,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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return getMOVL(DAG, dl, VT, V2, V1);
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}
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if (X86::isUNPCKH_v_undef_Mask(SVOp) ||
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X86::isUNPCKLMask(SVOp) ||
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if (X86::isUNPCKLMask(SVOp) ||
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X86::isUNPCKHMask(SVOp))
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return Op;
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@ -5316,8 +5350,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const {
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// FIXME: this seems wrong.
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SDValue NewOp = CommuteVectorShuffle(SVOp, DAG);
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ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp);
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if (X86::isUNPCKH_v_undef_Mask(NewSVOp) ||
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X86::isUNPCKLMask(NewSVOp) ||
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if (X86::isUNPCKLMask(NewSVOp) ||
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X86::isUNPCKHMask(NewSVOp))
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return NewOp;
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}
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