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Annotate remaining IIC_BIN_* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177539 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -932,7 +932,8 @@ class BinOpMI8<string mnemonic, X86TypeInfo typeinfo,
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Format f, list<dag> pattern>
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: ITy<0x82, f, typeinfo,
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(outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src),
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mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> {
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mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>,
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Sched<[WriteALULd, WriteRMW]> {
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let ImmT = Imm8; // Always 8-bit immediate.
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}
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@ -964,7 +965,7 @@ class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo,
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Register areg, string operands>
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: ITy<opcode, RawFrm, typeinfo,
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(outs), (ins typeinfo.ImmOperand:$src),
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mnemonic, operands, []> {
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mnemonic, operands, []>, Sched<[WriteALU]> {
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let ImmT = typeinfo.ImmEncoding;
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let Uses = [areg];
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let Defs = [areg];
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@ -1250,7 +1251,7 @@ let isCompare = 1, Defs = [EFLAGS] in {
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// register class is constrained to GR8_NOREX.
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let isPseudo = 1 in
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def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask),
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"", [], IIC_BIN_NONMEM>;
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"", [], IIC_BIN_NONMEM>, Sched<[WriteALU]>;
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}
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//===----------------------------------------------------------------------===//
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@ -1313,6 +1314,7 @@ let Predicates = [HasBMI2] in {
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// ADCX Instruction
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//
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let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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let SchedRW = [WriteALU] in {
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def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"adcx{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8, OpSize;
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@ -1320,8 +1322,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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def ADCX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"adcx{q}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8, OpSize, REX_W, Requires<[In64BitMode]>;
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} // SchedRW
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let mayLoad = 1 in {
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let mayLoad = 1, SchedRW = [WriteALULd] in {
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def ADCX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"adcx{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_MEM>, T8, OpSize;
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@ -1336,6 +1339,7 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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// ADOX Instruction
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//
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let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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let SchedRW = [WriteALU] in {
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def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
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"adox{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8XS;
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@ -1343,8 +1347,9 @@ let hasSideEffects = 0, Predicates = [HasADX], Defs = [EFLAGS] in {
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def ADOX64rr : I<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
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"adox{q}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_NONMEM>, T8XS, REX_W, Requires<[In64BitMode]>;
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} // SchedRW
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let mayLoad = 1 in {
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let mayLoad = 1, SchedRW = [WriteALULd] in {
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def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
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"adox{l}\t{$src, $dst|$dst, $src}",
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[], IIC_BIN_MEM>, T8XS;
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