mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-27 13:29:50 +00:00
Revert "pre-RA-sched: fix TargetOpcode usage"
This reverts commit 06091513c2
.
The code is obviously wrong, but the trivial fix causes
inefficient code generation on X86. Somebody with more
knowledge of the code needs to take a look here.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177529 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
fa963a885c
commit
61aba54f2c
@ -1894,15 +1894,12 @@ unsigned RegReductionPQBase::getNodePriority(const SUnit *SU) const {
|
||||
// CopyToReg should be close to its uses to facilitate coalescing and
|
||||
// avoid spilling.
|
||||
return 0;
|
||||
if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
|
||||
Opc = SU->getNode()->getMachineOpcode();
|
||||
if (Opc == TargetOpcode::EXTRACT_SUBREG ||
|
||||
Opc == TargetOpcode::SUBREG_TO_REG ||
|
||||
Opc == TargetOpcode::INSERT_SUBREG)
|
||||
// EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
|
||||
// close to their uses to facilitate coalescing.
|
||||
return 0;
|
||||
}
|
||||
if (Opc == TargetOpcode::EXTRACT_SUBREG ||
|
||||
Opc == TargetOpcode::SUBREG_TO_REG ||
|
||||
Opc == TargetOpcode::INSERT_SUBREG)
|
||||
// EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
|
||||
// close to their uses to facilitate coalescing.
|
||||
return 0;
|
||||
if (SU->NumSuccs == 0 && SU->NumPreds != 0)
|
||||
// If SU does not have a register use, i.e. it doesn't produce a value
|
||||
// that would be consumed (e.g. store), then it terminates a chain of
|
||||
@ -2588,15 +2585,12 @@ static bool canEnableCoalescing(SUnit *SU) {
|
||||
// avoid spilling.
|
||||
return true;
|
||||
|
||||
if (SU->getNode() && SU->getNode()->isMachineOpcode()) {
|
||||
Opc = SU->getNode()->getMachineOpcode();
|
||||
if (Opc == TargetOpcode::EXTRACT_SUBREG ||
|
||||
Opc == TargetOpcode::SUBREG_TO_REG ||
|
||||
Opc == TargetOpcode::INSERT_SUBREG)
|
||||
// EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
|
||||
// close to their uses to facilitate coalescing.
|
||||
return true;
|
||||
}
|
||||
if (Opc == TargetOpcode::EXTRACT_SUBREG ||
|
||||
Opc == TargetOpcode::SUBREG_TO_REG ||
|
||||
Opc == TargetOpcode::INSERT_SUBREG)
|
||||
// EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
|
||||
// close to their uses to facilitate coalescing.
|
||||
return true;
|
||||
|
||||
if (SU->NumPreds == 0 && SU->NumSuccs != 0)
|
||||
// If SU does not have a register def, schedule it close to its uses
|
||||
|
Loading…
Reference in New Issue
Block a user