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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-20 10:30:03 +00:00
80-column, tab characters, comment fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207473 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
4ffd83b92b
commit
3756feaadc
@ -222,7 +222,7 @@ unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
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if (!DisableRedZone &&
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(Subtarget.isPPC64() || // 32-bit SVR4, no stack-
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!Subtarget.isSVR4ABI() || // allocated locals.
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FrameSize == 0) &&
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FrameSize == 0) &&
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FrameSize <= 224 && // Fits in red zone.
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!MFI->hasVarSizedObjects() && // No dynamic alloca.
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!MFI->adjustsStack() && // No calls.
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@ -281,8 +281,8 @@ bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
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// Naked functions have no stack frame pushed, so we don't have a frame
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// pointer.
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if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
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Attribute::Naked))
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if (MF.getFunction()->getAttributes().hasAttribute(
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AttributeSet::FunctionIndex, Attribute::Naked))
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return false;
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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@ -426,7 +426,8 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
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assert(FPIndex && "No Frame Pointer Save Slot!");
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FPOffset = FFI->getObjectOffset(FPIndex);
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} else {
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FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
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FPOffset =
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PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
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}
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}
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@ -712,7 +713,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
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assert(FPIndex && "No Frame Pointer Save Slot!");
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FPOffset = FFI->getObjectOffset(FPIndex);
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} else {
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FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
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FPOffset =
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PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
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}
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}
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@ -930,9 +932,9 @@ PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
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MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
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}
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// For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
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// For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
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// function uses CR 2, 3, or 4.
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if (!isPPC64 && !isDarwinABI &&
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if (!isPPC64 && !isDarwinABI &&
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(MRI.isPhysRegUsed(PPC::CR2) ||
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MRI.isPhysRegUsed(PPC::CR3) ||
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MRI.isPhysRegUsed(PPC::CR4))) {
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@ -1106,10 +1108,10 @@ void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
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unsigned Reg = CSI[i].getReg();
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if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
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// Leave Darwin logic as-is.
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|| (!Subtarget.isSVR4ABI() &&
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(PPC::CRBITRCRegClass.contains(Reg) ||
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PPC::CRRCRegClass.contains(Reg)))) {
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// Leave Darwin logic as-is.
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|| (!Subtarget.isSVR4ABI() &&
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(PPC::CRBITRCRegClass.contains(Reg) ||
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PPC::CRRCRegClass.contains(Reg)))) {
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int FI = CSI[i].getFrameIdx();
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FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
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@ -1190,11 +1192,11 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
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}
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}
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bool
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bool
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PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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// Currently, this function only handles SVR4 32- and 64-bit ABIs.
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// Return false otherwise to maintain pre-existing behavior.
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@ -1207,7 +1209,7 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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DebugLoc DL;
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bool CRSpilled = false;
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MachineInstrBuilder CRMIB;
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// Only Darwin actually uses the VRSAVE register, but it can still appear
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@ -1237,21 +1239,21 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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CRSpilled = true;
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FuncInfo->setSpillsCR();
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// 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
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// the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
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CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
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// 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
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// the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
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CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
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.addReg(Reg, RegState::ImplicitKill);
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MBB.insert(MI, CRMIB);
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MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
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.addReg(PPC::R12,
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getKillRegState(true)),
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CSI[i].getFrameIdx()));
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MBB.insert(MI, CRMIB);
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MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
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.addReg(PPC::R12,
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getKillRegState(true)),
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CSI[i].getFrameIdx()));
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}
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} else {
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(MBB, MI, Reg, true,
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CSI[i].getFrameIdx(), RC, TRI);
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CSI[i].getFrameIdx(), RC, TRI);
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}
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}
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return true;
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@ -1260,8 +1262,8 @@ PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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static void
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restoreCRs(bool isPPC64, bool is31,
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bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
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MachineFunction *MF = MBB.getParent();
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const PPCInstrInfo &TII =
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@ -1275,12 +1277,12 @@ restoreCRs(bool isPPC64, bool is31,
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else {
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// 32-bit: FP-relative
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MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
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PPC::R12),
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CSI[CSIIndex].getFrameIdx()));
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PPC::R12),
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CSI[CSIIndex].getFrameIdx()));
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RestoreOp = PPC::MTOCRF;
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MoveReg = PPC::R12;
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}
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if (CR2Spilled)
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MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
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.addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
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@ -1335,11 +1337,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MBB.erase(I);
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}
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bool
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bool
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PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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// Currently, this function only handles SVR4 32- and 64-bit ABIs.
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// Return false otherwise to maintain pre-existing behavior.
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@ -1387,20 +1389,20 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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// When we first encounter a non-CR register after seeing at
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// least one CR register, restore all spilled CRs together.
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if ((CR2Spilled || CR3Spilled || CR4Spilled)
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&& !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
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&& !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
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bool is31 = needsFP(*MF);
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restoreCRs(Subtarget.isPPC64(), is31,
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CR2Spilled, CR3Spilled, CR4Spilled,
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MBB, I, CSI, CSIIndex);
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CR2Spilled = CR3Spilled = CR4Spilled = false;
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MBB, I, CSI, CSIIndex);
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CR2Spilled = CR3Spilled = CR4Spilled = false;
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}
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// Default behavior for non-CR saves.
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
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RC, TRI);
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RC, TRI);
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assert(I != MBB.begin() &&
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"loadRegFromStackSlot didn't insert any code!");
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"loadRegFromStackSlot didn't insert any code!");
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}
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// Insert in reverse order.
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@ -1409,16 +1411,15 @@ PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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else {
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I = BeforeI;
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++I;
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}
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}
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}
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// If we haven't yet spilled the CRs, do so now.
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if (CR2Spilled || CR3Spilled || CR4Spilled) {
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bool is31 = needsFP(*MF);
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bool is31 = needsFP(*MF);
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restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
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MBB, I, CSI, CSIIndex);
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MBB, I, CSI, CSIIndex);
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}
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return true;
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}
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