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This patch addresses a PPC64 ELF issue with passing parameters consisting of
structs having size 3, 5, 6, or 7. Such a struct must be passed and received as right-justified within its register or memory slot. The problem is only present for structs that are passed in registers. Previously, as part of a patch handling all structs of size less than 8, I added logic to rotate the incoming register so that the struct was left- justified prior to storing the whole register. This was incorrect because the address of the parameter had already been adjusted earlier to point to the right-adjusted value in the storage slot. Essentially I had accidentally accounted for the right-adjustment twice. In this patch, I removed the incorrect logic and reorganized the code to make the flow clearer. The removal of the rotates changes the expected code generation, so test case structsinregs.ll has been modified to reflect this. I also added a new test case, jaggedstructs.ll, to demonstrate that structs of these sizes can now be properly received and passed. I've built and tested the code on powerpc64-unknown-linux-gnu with no new regressions. I also ran the GCC compatibility test suite and verified that earlier problems with these structs are now resolved, with no new regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166680 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Schmidt
parent
6e8946c528
commit
37900c5dcb
@ -2084,25 +2084,42 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
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int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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InVals.push_back(FIN);
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if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
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if (ObjSize < 8) {
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if (GPR_idx != Num_GPR_Regs) {
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unsigned VReg;
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VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
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unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
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EVT ObjType = (ObjSize == 1 ? MVT::i8 :
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(ObjSize == 2 ? MVT::i16 : MVT::i32));
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SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(FuncArg,
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CurArgOffset),
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ObjType, false, false, 0);
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SDValue Store;
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if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
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EVT ObjType = (ObjSize == 1 ? MVT::i8 :
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(ObjSize == 2 ? MVT::i16 : MVT::i32));
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Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(FuncArg, CurArgOffset),
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ObjType, false, false, 0);
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} else {
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// For sizes that don't fit a truncating store (3, 5, 6, 7),
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// store the whole register as-is to the parameter save area
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// slot. The address of the parameter was already calculated
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// above (InVals.push_back(FIN)) to be the right-justified
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// offset within the slot. For this store, we need a new
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// frame index that points at the beginning of the slot.
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int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(FuncArg, ArgOffset),
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false, false, 0);
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}
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MemOps.push_back(Store);
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++GPR_idx;
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}
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// Whether we copied from a register or not, advance the offset
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// into the parameter save area by a full doubleword.
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ArgOffset += PtrByteSize;
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continue;
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}
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for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
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// Store whatever pieces of the object are in registers
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// to memory. ArgOffset will be the address of the beginning
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@ -2113,16 +2130,7 @@ PPCTargetLowering::LowerFormalArguments_64SVR4(
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int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
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SDValue Shifted = Val;
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// For 64-bit SVR4, small structs come in right-adjusted.
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// Shift them left so the following logic works as expected.
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if (ObjSize < 8) {
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SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT);
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Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt);
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}
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN,
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(FuncArg, ArgOffset),
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false, false, 0);
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MemOps.push_back(Store);
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48
test/CodeGen/PowerPC/jaggedstructs.ll
Normal file
48
test/CodeGen/PowerPC/jaggedstructs.ll
Normal file
@ -0,0 +1,48 @@
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; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
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; This tests receiving and re-passing parameters consisting of structures
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; of size 3, 5, 6, and 7. They are to be found/placed right-adjusted in
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; the parameter registers.
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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%struct.S3 = type { [3 x i8] }
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%struct.S5 = type { [5 x i8] }
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%struct.S6 = type { [6 x i8] }
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%struct.S7 = type { [7 x i8] }
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define void @test(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7) nounwind {
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entry:
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call void @check(%struct.S3* byval %s3, %struct.S5* byval %s5, %struct.S6* byval %s6, %struct.S7* byval %s7)
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ret void
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}
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; CHECK: std 6, 216(1)
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; CHECK: std 5, 208(1)
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; CHECK: std 4, 200(1)
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; CHECK: std 3, 192(1)
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; CHECK: lbz {{[0-9]+}}, 199(1)
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; CHECK: stb {{[0-9]+}}, 55(1)
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; CHECK: lhz {{[0-9]+}}, 197(1)
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; CHECK: sth {{[0-9]+}}, 53(1)
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; CHECK: lbz {{[0-9]+}}, 207(1)
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; CHECK: stb {{[0-9]+}}, 63(1)
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; CHECK: lwz {{[0-9]+}}, 203(1)
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; CHECK: stw {{[0-9]+}}, 59(1)
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; CHECK: lhz {{[0-9]+}}, 214(1)
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; CHECK: sth {{[0-9]+}}, 70(1)
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; CHECK: lwz {{[0-9]+}}, 210(1)
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; CHECK: stw {{[0-9]+}}, 66(1)
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; CHECK: lbz {{[0-9]+}}, 223(1)
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; CHECK: stb {{[0-9]+}}, 79(1)
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; CHECK: lhz {{[0-9]+}}, 221(1)
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; CHECK: sth {{[0-9]+}}, 77(1)
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; CHECK: lwz {{[0-9]+}}, 217(1)
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; CHECK: stw {{[0-9]+}}, 73(1)
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; CHECK: ld 6, 72(1)
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; CHECK: ld 5, 64(1)
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; CHECK: ld 4, 56(1)
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; CHECK: ld 3, 48(1)
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declare void @check(%struct.S3* byval, %struct.S5* byval, %struct.S6* byval, %struct.S7* byval)
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@ -188,17 +188,13 @@ entry:
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%add13 = add nsw i32 %add11, %6
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ret i32 %add13
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; CHECK: sldi 9, 9, 8
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; CHECK: sldi 8, 8, 16
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; CHECK: sldi 7, 7, 24
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; CHECK: sldi 5, 5, 40
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; CHECK: stw 6, 76(1)
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; CHECK: sth 4, 62(1)
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; CHECK: stb 3, 55(1)
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; CHECK: std 9, 96(1)
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; CHECK: std 8, 88(1)
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; CHECK: std 7, 80(1)
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; CHECK: stw 6, 76(1)
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; CHECK: std 5, 64(1)
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; CHECK: sth 4, 62(1)
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; CHECK: stb 3, 55(1)
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; CHECK: lbz {{[0-9]+}}, 85(1)
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; CHECK: lbz {{[0-9]+}}, 86(1)
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; CHECK: lbz {{[0-9]+}}, 83(1)
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