mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
Implement the full V8 ABI for incoming arguments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24825 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
eee99bd459
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384e5efc0e
@ -13,6 +13,7 @@
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -129,31 +130,42 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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computeRegisterProperties();
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}
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// in FP registers for fastcc functions.
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std::vector<SDOperand>
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SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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static const unsigned GPR[] = {
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static const unsigned ArgRegs[] = {
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V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
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};
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unsigned ArgNo = 0;
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const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = 68;
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SDOperand Root = DAG.getRoot();
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std::vector<SDOperand> OutChains;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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MVT::ValueType ObjectVT = getValueType(I->getType());
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assert(ArgNo < 6 && "Only args in regs for now");
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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// TODO: MVT::i64 & FP
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// TODO: FP
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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case MVT::i32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VReg);
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SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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DAG.setRoot(Arg.getValue(1));
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
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: ISD::AssertZext;
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@ -162,23 +174,126 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
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}
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ArgValues.push_back(Arg);
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break;
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand Load;
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if (ObjectVT == MVT::i32) {
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Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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} else {
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unsigned LoadOp =
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I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
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DAG.getSrcValue(0), ObjectVT);
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}
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case MVT::i64: {
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ArgValues.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::f32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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// FP value is passed in an integer register.
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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// We use the stack space that is already reserved for this reg.
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand SV = DAG.getSrcValue(0);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
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Arg, FIPtr, SV);
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ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
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}
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
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((CurArgReg-ArgRegs) & 1) == 0) {
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// If this is a double argument and the whole thing lives on the stack,
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// and the argument is aligned, load the double straight from the stack.
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// We can't do a load in cases like void foo([6ints], int,double),
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// because the double wouldn't be aligned!
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
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DAG.getSrcValue(0)));
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} else {
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SDOperand HiVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VRegHi);
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unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VRegLo);
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SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
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SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
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DAG.setRoot(ArgHi.getValue(1));
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ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
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break;
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MF.addLiveIn(*CurArgReg++, VRegHi);
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HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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}
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SDOperand LoVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VRegLo);
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LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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}
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// Compose the two halves together into an i64 unit.
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SDOperand WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
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if (ObjectVT == MVT::i64) {
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// If we are emitting an i64, this is what we want.
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ArgValues.push_back(WholeValue);
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} else {
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assert(ObjectVT == MVT::f64);
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// Otherwise, emit a store to the stack and reload into FPR.
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int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand SV = DAG.getSrcValue(0);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
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WholeValue, FIPtr, SV);
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ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
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}
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}
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ArgOffset += 8;
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break;
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}
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}
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assert(!F.isVarArg() && "Unimp");
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// Store remaining ArgRegs to the stack if this is a varargs function.
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if (F.getFunctionType()->isVarArg()) {
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for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg, VReg);
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SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
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Arg, FIPtr, DAG.getSrcValue(0)));
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ArgOffset += 4;
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}
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}
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if (!OutChains.empty())
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DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
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// Finally, inform the code generator which regs we return values in.
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switch (getValueType(F.getReturnType())) {
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@ -367,7 +367,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
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// FIXME: We could avoid storing any args onto the stack that don't
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// need to be in memory, because they come before the ellipsis in the
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// parameter list (and thus could never be accessed through va_arg).
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if (LF->getFunctionType ()->isVarArg ()) {
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if (LF->getFunctionType()->isVarArg()) {
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for (unsigned i = 0; i < 6; ++i) {
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int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
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assert (IAR != IAREnd
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@ -13,6 +13,7 @@
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#include "SparcV8.h"
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#include "SparcV8TargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@ -129,31 +130,42 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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computeRegisterProperties();
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}
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/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
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/// either one or two GPRs, including FP values. TODO: we should pass FP values
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/// in FP registers for fastcc functions.
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std::vector<SDOperand>
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SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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static const unsigned GPR[] = {
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static const unsigned ArgRegs[] = {
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V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
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};
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unsigned ArgNo = 0;
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const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
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unsigned ArgOffset = 68;
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SDOperand Root = DAG.getRoot();
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std::vector<SDOperand> OutChains;
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for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
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MVT::ValueType ObjectVT = getValueType(I->getType());
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assert(ArgNo < 6 && "Only args in regs for now");
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switch (ObjectVT) {
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default: assert(0 && "Unhandled argument type!");
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// TODO: MVT::i64 & FP
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// TODO: FP
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32: {
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case MVT::i32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VReg);
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SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
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DAG.setRoot(Arg.getValue(1));
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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if (ObjectVT != MVT::i32) {
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unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
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: ISD::AssertZext;
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@ -162,23 +174,126 @@ SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
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Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
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}
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ArgValues.push_back(Arg);
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break;
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand Load;
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if (ObjectVT == MVT::i32) {
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Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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} else {
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unsigned LoadOp =
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I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
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Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
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DAG.getSrcValue(0), ObjectVT);
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}
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case MVT::i64: {
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ArgValues.push_back(Load);
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}
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ArgOffset += 4;
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break;
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case MVT::f32:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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// FP value is passed in an integer register.
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unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VReg);
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SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
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// We use the stack space that is already reserved for this reg.
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand SV = DAG.getSrcValue(0);
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SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
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Arg, FIPtr, SV);
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ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV));
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}
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ArgOffset += 4;
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break;
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case MVT::i64:
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case MVT::f64:
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if (I->use_empty()) { // Argument is dead.
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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if (CurArgReg < ArgRegEnd) ++CurArgReg;
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ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
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} else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
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((CurArgReg-ArgRegs) & 1) == 0) {
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// If this is a double argument and the whole thing lives on the stack,
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// and the argument is aligned, load the double straight from the stack.
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// We can't do a load in cases like void foo([6ints], int,double),
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// because the double wouldn't be aligned!
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
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DAG.getSrcValue(0)));
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} else {
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SDOperand HiVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VRegHi);
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unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(GPR[ArgNo++], VRegLo);
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SDOperand ArgLo = DAG.getCopyFromReg(DAG.getRoot(), VRegLo, MVT::i32);
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SDOperand ArgHi = DAG.getCopyFromReg(ArgLo.getValue(1), VRegHi, MVT::i32);
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DAG.setRoot(ArgHi.getValue(1));
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ArgValues.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::i64, ArgLo, ArgHi));
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break;
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MF.addLiveIn(*CurArgReg++, VRegHi);
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HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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}
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SDOperand LoVal;
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if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
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unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
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MF.addLiveIn(*CurArgReg++, VRegLo);
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LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
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} else {
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int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
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}
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// Compose the two halves together into an i64 unit.
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SDOperand WholeValue =
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DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
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if (ObjectVT == MVT::i64) {
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// If we are emitting an i64, this is what we want.
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ArgValues.push_back(WholeValue);
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} else {
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assert(ObjectVT == MVT::f64);
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// Otherwise, emit a store to the stack and reload into FPR.
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int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
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SDOperand SV = DAG.getSrcValue(0);
|
||||
SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root,
|
||||
WholeValue, FIPtr, SV);
|
||||
ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV));
|
||||
}
|
||||
}
|
||||
ArgOffset += 8;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
assert(!F.isVarArg() && "Unimp");
|
||||
// Store remaining ArgRegs to the stack if this is a varargs function.
|
||||
if (F.getFunctionType()->isVarArg()) {
|
||||
for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
|
||||
unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
|
||||
MF.addLiveIn(*CurArgReg, VReg);
|
||||
SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
|
||||
|
||||
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
|
||||
|
||||
OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
|
||||
Arg, FIPtr, DAG.getSrcValue(0)));
|
||||
ArgOffset += 4;
|
||||
}
|
||||
}
|
||||
|
||||
if (!OutChains.empty())
|
||||
DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
|
||||
|
||||
// Finally, inform the code generator which regs we return values in.
|
||||
switch (getValueType(F.getReturnType())) {
|
||||
|
@ -367,7 +367,7 @@ void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
|
||||
// FIXME: We could avoid storing any args onto the stack that don't
|
||||
// need to be in memory, because they come before the ellipsis in the
|
||||
// parameter list (and thus could never be accessed through va_arg).
|
||||
if (LF->getFunctionType ()->isVarArg ()) {
|
||||
if (LF->getFunctionType()->isVarArg()) {
|
||||
for (unsigned i = 0; i < 6; ++i) {
|
||||
int FI = F->getFrameInfo()->CreateFixedObject(4, ArgOffset);
|
||||
assert (IAR != IAREnd
|
||||
|
Loading…
Reference in New Issue
Block a user