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[Sparc] Implement JIT for SPARC.
No new testcases. However, this patch makes all supported JIT testcases in test/ExecutionEngine pass on Sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192176 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
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@ -21,6 +21,8 @@ add_llvm_target(SparcCodeGen
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SparcSubtarget.cpp
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SparcTargetMachine.cpp
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SparcSelectionDAGInfo.cpp
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SparcJITInfo.cpp
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SparcCodeEmitter.cpp
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)
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add_dependencies(LLVMSparcCodeGen SparcCommonTableGen intrinsics_gen)
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@ -23,6 +23,7 @@ type = TargetGroup
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name = Sparc
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parent = Target
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has_asmprinter = 1
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has_jit = 1
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[component_1]
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type = Library
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@ -26,6 +26,8 @@ namespace llvm {
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FunctionPass *createSparcISelDag(SparcTargetMachine &TM);
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FunctionPass *createSparcDelaySlotFillerPass(TargetMachine &TM);
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FunctionPass *createSparcJITCodeEmitterPass(SparcTargetMachine &TM,
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JITCodeEmitter &JCE);
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} // end namespace llvm;
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245
lib/Target/Sparc/SparcCodeEmitter.cpp
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245
lib/Target/Sparc/SparcCodeEmitter.cpp
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@ -0,0 +1,245 @@
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//===-- Sparc/SparcCodeEmitter.cpp - Convert Sparc Code to Machine Code ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===---------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the Sparc machine instructions
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// into relocatable machine code.
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//
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//===---------------------------------------------------------------------===//
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#define DEBUG_TYPE "jit"
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#include "Sparc.h"
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#include "MCTargetDesc/SparcBaseInfo.h"
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#include "SparcRelocations.h"
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#include "SparcTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class SparcCodeEmitter : public MachineFunctionPass {
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SparcJITInfo *JTI;
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const SparcInstrInfo *II;
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const DataLayout *TD;
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const SparcSubtarget *Subtarget;
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TargetMachine &TM;
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JITCodeEmitter &MCE;
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const std::vector<MachineConstantPoolEntry> *MCPEs;
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bool IsPIC;
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineModuleInfo> ();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static char ID;
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public:
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SparcCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(ID), JTI(0), II(0), TD(0),
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TM(tm), MCE(mce), MCPEs(0),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "Sparc Machine Code Emitter";
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}
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
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void emitInstruction(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB);
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private:
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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void emitWord(unsigned Word);
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unsigned getRelocation(const MachineInstr &MI,
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const MachineOperand &MO) const;
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void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc) const;
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
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void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc) const;
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};
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} // end anonymous namespace.
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char SparcCodeEmitter::ID = 0;
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bool SparcCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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SparcTargetMachine &Target = static_cast<SparcTargetMachine &>(
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const_cast<TargetMachine &>(MF.getTarget()));
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JTI = Target.getJITInfo();
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II = Target.getInstrInfo();
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TD = Target.getDataLayout();
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Subtarget = &TM.getSubtarget<SparcSubtarget> ();
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MCPEs = &MF.getConstantPool()->getConstants();
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JTI->Initialize(MF, IsPIC);
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MCE.setModuleInfo(&getAnalysis<MachineModuleInfo> ());
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do {
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DEBUG(errs() << "JITTing function '"
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<< MF.getName() << "'\n");
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB){
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::instr_iterator I = MBB->instr_begin(),
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E = MBB->instr_end(); I != E;)
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emitInstruction(*I++, *MBB);
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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void SparcCodeEmitter::emitInstruction(MachineBasicBlock::instr_iterator MI,
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MachineBasicBlock &MBB) {
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DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << *MI);
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MCE.processDebugLoc(MI->getDebugLoc(), true);
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++NumEmitted;
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switch (MI->getOpcode()) {
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default: {
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emitWord(getBinaryCodeForInstr(*MI));
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break;
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}
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case TargetOpcode::INLINEASM: {
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// We allow inline assembler nodes with empty bodies - they can
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// implicitly define registers, which is ok for JIT.
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if (MI->getOperand(0).getSymbolName()[0]) {
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report_fatal_error("JIT does not support inline asm!");
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}
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break;
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}
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case TargetOpcode::PROLOG_LABEL:
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case TargetOpcode::EH_LABEL: {
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MCE.emitLabel(MI->getOperand(0).getMCSymbol());
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break;
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}
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL: {
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// Do nothing.
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break;
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}
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case SP::GETPCX: {
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report_fatal_error("JIT does not support pseudo instruction GETPCX yet!");
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break;
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}
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}
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MCE.processDebugLoc(MI->getDebugLoc(), false);
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}
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void SparcCodeEmitter::emitWord(unsigned Word) {
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DEBUG(errs() << " 0x";
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errs().write_hex(Word) << "\n");
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MCE.emitWordBE(Word);
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}
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/// getMachineOpValue - Return binary encoding of operand. If the machine
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/// operand requires relocation, record the relocation and return zero.
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unsigned SparcCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const {
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if (MO.isReg())
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return TM.getRegisterInfo()->getEncodingValue(MO.getReg());
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else if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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else if (MO.isGlobal())
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emitGlobalAddress(MO.getGlobal(), getRelocation(MI, MO));
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else if (MO.isSymbol())
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emitExternalSymbolAddress(MO.getSymbolName(), getRelocation(MI, MO));
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else if (MO.isCPI())
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emitConstPoolAddress(MO.getIndex(), getRelocation(MI, MO));
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else if (MO.isMBB())
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emitMachineBasicBlock(MO.getMBB(), getRelocation(MI, MO));
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else
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llvm_unreachable("Unable to encode MachineOperand!");
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return 0;
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}
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unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
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const MachineOperand &MO) const {
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unsigned TF = MO.getTargetFlags();
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switch (TF) {
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default:
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case SPII::MO_NO_FLAG: break;
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case SPII::MO_LO: return SP::reloc_sparc_lo;
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case SPII::MO_HI: return SP::reloc_sparc_hi;
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case SPII::MO_H44:
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case SPII::MO_M44:
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case SPII::MO_L44:
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case SPII::MO_HH:
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case SPII::MO_HM: assert(0 && "FIXME: Implement Medium/Large code model.");
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}
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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default: break;
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case SP::CALL: return SP::reloc_sparc_pc30;
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case SP::BA:
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case SP::BCOND:
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case SP::FBCOND: return SP::reloc_sparc_pc22;
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case SP::BPXCC: return SP::reloc_sparc_pc19;
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}
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llvm_unreachable("unknown reloc!");
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}
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void SparcCodeEmitter::emitGlobalAddress(const GlobalValue *GV,
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unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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const_cast<GlobalValue *>(GV), 0,
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true));
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}
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void SparcCodeEmitter::
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emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES, 0, 0));
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}
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void SparcCodeEmitter::
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emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, 0, false));
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}
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void SparcCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
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unsigned Reloc) const {
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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Reloc, BB));
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}
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/// createSparcJITCodeEmitterPass - Return a pass that emits the collected Sparc
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/// code to the specified MCE object.
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FunctionPass *llvm::createSparcJITCodeEmitterPass(SparcTargetMachine &TM,
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JITCodeEmitter &JCE) {
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return new SparcCodeEmitter(TM, JCE);
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}
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#include "SparcGenCodeEmitter.inc"
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@ -1668,6 +1668,7 @@ SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const {
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switch(getTargetMachine().getCodeModel()) {
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default:
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llvm_unreachable("Unsupported absolute code model");
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case CodeModel::JITDefault:
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case CodeModel::Small:
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// abs32.
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return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG);
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@ -394,63 +394,63 @@ def LDQFri : F3_2<3, 0b100010,
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// Section B.4 - Store Integer Instructions, p. 95
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def STBrr : F3_1<3, 0b000101,
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(outs), (ins MEMrr:$addr, IntRegs:$src),
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"stb $src, [$addr]",
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[(truncstorei8 i32:$src, ADDRrr:$addr)]>;
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(outs), (ins MEMrr:$addr, IntRegs:$rd),
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"stb $rd, [$addr]",
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[(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
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def STBri : F3_2<3, 0b000101,
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(outs), (ins MEMri:$addr, IntRegs:$src),
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"stb $src, [$addr]",
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[(truncstorei8 i32:$src, ADDRri:$addr)]>;
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(outs), (ins MEMri:$addr, IntRegs:$rd),
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"stb $rd, [$addr]",
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[(truncstorei8 i32:$rd, ADDRri:$addr)]>;
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def STHrr : F3_1<3, 0b000110,
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(outs), (ins MEMrr:$addr, IntRegs:$src),
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"sth $src, [$addr]",
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[(truncstorei16 i32:$src, ADDRrr:$addr)]>;
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(outs), (ins MEMrr:$addr, IntRegs:$rd),
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"sth $rd, [$addr]",
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[(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
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def STHri : F3_2<3, 0b000110,
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(outs), (ins MEMri:$addr, IntRegs:$src),
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"sth $src, [$addr]",
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[(truncstorei16 i32:$src, ADDRri:$addr)]>;
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(outs), (ins MEMri:$addr, IntRegs:$rd),
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"sth $rd, [$addr]",
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[(truncstorei16 i32:$rd, ADDRri:$addr)]>;
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def STrr : F3_1<3, 0b000100,
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(outs), (ins MEMrr:$addr, IntRegs:$src),
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"st $src, [$addr]",
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[(store i32:$src, ADDRrr:$addr)]>;
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(outs), (ins MEMrr:$addr, IntRegs:$rd),
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"st $rd, [$addr]",
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[(store i32:$rd, ADDRrr:$addr)]>;
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def STri : F3_2<3, 0b000100,
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(outs), (ins MEMri:$addr, IntRegs:$src),
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"st $src, [$addr]",
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[(store i32:$src, ADDRri:$addr)]>;
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(outs), (ins MEMri:$addr, IntRegs:$rd),
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"st $rd, [$addr]",
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[(store i32:$rd, ADDRri:$addr)]>;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100,
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(outs), (ins MEMrr:$addr, FPRegs:$src),
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"st $src, [$addr]",
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[(store f32:$src, ADDRrr:$addr)]>;
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(outs), (ins MEMrr:$addr, FPRegs:$rd),
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"st $rd, [$addr]",
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[(store f32:$rd, ADDRrr:$addr)]>;
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def STFri : F3_2<3, 0b100100,
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(outs), (ins MEMri:$addr, FPRegs:$src),
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"st $src, [$addr]",
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[(store f32:$src, ADDRri:$addr)]>;
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(outs), (ins MEMri:$addr, FPRegs:$rd),
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"st $rd, [$addr]",
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[(store f32:$rd, ADDRri:$addr)]>;
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def STDFrr : F3_1<3, 0b100111,
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(outs), (ins MEMrr:$addr, DFPRegs:$src),
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"std $src, [$addr]",
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[(store f64:$src, ADDRrr:$addr)]>;
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(outs), (ins MEMrr:$addr, DFPRegs:$rd),
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"std $rd, [$addr]",
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[(store f64:$rd, ADDRrr:$addr)]>;
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def STDFri : F3_2<3, 0b100111,
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(outs), (ins MEMri:$addr, DFPRegs:$src),
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"std $src, [$addr]",
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[(store f64:$src, ADDRri:$addr)]>;
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(outs), (ins MEMri:$addr, DFPRegs:$rd),
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"std $rd, [$addr]",
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[(store f64:$rd, ADDRri:$addr)]>;
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def STQFrr : F3_1<3, 0b100110,
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(outs), (ins MEMrr:$addr, QFPRegs:$src),
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"stq $src, [$addr]",
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[(store f128:$src, ADDRrr:$addr)]>,
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(outs), (ins MEMrr:$addr, QFPRegs:$rd),
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"stq $rd, [$addr]",
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[(store f128:$rd, ADDRrr:$addr)]>,
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Requires<[HasV9, HasHardQuad]>;
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def STQFri : F3_2<3, 0b100110,
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(outs), (ins MEMri:$addr, QFPRegs:$src),
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"stq $src, [$addr]",
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[(store f128:$src, ADDRri:$addr)]>,
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(outs), (ins MEMri:$addr, QFPRegs:$rd),
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"stq $rd, [$addr]",
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[(store f128:$rd, ADDRri:$addr)]>,
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Requires<[HasV9, HasHardQuad]>;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100,
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(outs IntRegs:$dst), (ins i32imm:$src),
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"sethi $src, $dst",
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[(set i32:$dst, SETHIimm:$src)]>;
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(outs IntRegs:$rd), (ins i32imm:$imm22),
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"sethi $imm22, $rd",
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[(set i32:$rd, SETHIimm:$imm22)]>;
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// Section B.10 - NOP Instruction, p. 105
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// (It's a special case of SETHI)
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@ -505,12 +505,12 @@ let Defs = [ICC] in
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defm ADDCC : F3_12<"addcc", 0b010000, addc>;
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let Uses = [ICC], Defs = [ICC] in
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defm ADDX : F3_12<"addxcc", 0b001000, adde>;
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defm ADDX : F3_12<"addxcc", 0b011000, adde>;
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// Section B.15 - Subtract Instructions, p. 110
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defm SUB : F3_12 <"sub" , 0b000100, sub>;
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let Uses = [ICC], Defs = [ICC] in
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defm SUBX : F3_12 <"subxcc" , 0b001100, sube>;
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defm SUBX : F3_12 <"subxcc" , 0b011100, sube>;
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let Defs = [ICC] in
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defm SUBCC : F3_12 <"subcc", 0b010100, subc>;
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168
lib/Target/Sparc/SparcJITInfo.cpp
Normal file
168
lib/Target/Sparc/SparcJITInfo.cpp
Normal file
@ -0,0 +1,168 @@
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//===-- SparcJITInfo.cpp - Implement the Sparc JIT Interface --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the JIT interfaces for the Sparc target.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "jit"
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#include "SparcJITInfo.h"
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#include "SparcRelocations.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/Support/Memory.h"
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using namespace llvm;
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/// JITCompilerFunction - This contains the address of the JIT function used to
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||||
/// compile a function lazily.
|
||||
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
|
||||
|
||||
extern "C" void SparcCompilationCallback();
|
||||
|
||||
extern "C" {
|
||||
#if defined (__sparc__)
|
||||
asm(
|
||||
".text\n"
|
||||
"\t.align 4\n"
|
||||
"\t.global SparcCompilationCallback\n"
|
||||
"\t.type SparcCompilationCallback, #function\n"
|
||||
"SparcCompilationCallback:\n"
|
||||
// Save current register window.
|
||||
"\tsave %sp, -192, %sp\n"
|
||||
// stubaddr+4 is in %g1.
|
||||
"\tcall SparcCompilationCallbackC\n"
|
||||
"\t sub %g1, 4, %o0\n"
|
||||
// restore original register window and
|
||||
// copy %o0 to %g1
|
||||
"\t restore %o0, 0, %g1\n"
|
||||
// call the new stub
|
||||
"\tjmp %g1\n"
|
||||
"\t nop\n"
|
||||
"\t.size SparcCompilationCallback, .-SparcCompilationCallback"
|
||||
);
|
||||
|
||||
#else
|
||||
void SparcCompilationCallback() {
|
||||
llvm_unreachable(
|
||||
"Cannot call SparcCompilationCallback() on a non-sparc arch!");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#define HI(Val) (((unsigned)(Val)) >> 10)
|
||||
#define LO(Val) (((unsigned)(Val)) & 0x3FF)
|
||||
|
||||
#define SETHI_INST(imm, rd) (0x01000000 | ((rd) << 25) | ((imm) & 0x3FFFFF))
|
||||
#define JMP_INST(rs1, imm, rd) (0x80000000 | ((rd) << 25) | (0x38 << 19) \
|
||||
| ((rs1) << 14) | (1 << 13) | ((imm) & 0x1FFF))
|
||||
#define NOP_INST SETHI_INST(0, 0)
|
||||
|
||||
extern "C" void *SparcCompilationCallbackC(intptr_t StubAddr) {
|
||||
// Get the address of the compiled code for this function.
|
||||
intptr_t NewVal = (intptr_t) JITCompilerFunction((void*) StubAddr);
|
||||
|
||||
// Rewrite the function stub so that we don't end up here every time we
|
||||
// execute the call. We're replacing the first three instructions of the
|
||||
// stub with code that jumps to the compiled function:
|
||||
// sethi %hi(NewVal), %g1
|
||||
// jmp %g1+%lo(NewVal)
|
||||
// nop
|
||||
|
||||
*(intptr_t *)(StubAddr) = SETHI_INST(HI(NewVal), 1);
|
||||
*(intptr_t *)(StubAddr + 4) = JMP_INST(1, LO(NewVal), 0);
|
||||
*(intptr_t *)(StubAddr + 8) = NOP_INST;
|
||||
|
||||
sys::Memory::InvalidateInstructionCache((void*) StubAddr, 12);
|
||||
return (void*)StubAddr;
|
||||
}
|
||||
|
||||
void SparcJITInfo::replaceMachineCodeForFunction(void *Old, void *New) {
|
||||
assert(0 && "FIXME: Implement SparcJITInfo::replaceMachineCodeForFunction");
|
||||
}
|
||||
|
||||
|
||||
TargetJITInfo::StubLayout SparcJITInfo::getStubLayout() {
|
||||
// The stub contains 3 4-byte instructions, aligned at 4 bytes. See
|
||||
// emitFunctionStub for details.
|
||||
|
||||
StubLayout Result = { 3*4, 4 };
|
||||
return Result;
|
||||
}
|
||||
|
||||
void *SparcJITInfo::emitFunctionStub(const Function *F, void *Fn,
|
||||
JITCodeEmitter &JCE)
|
||||
{
|
||||
JCE.emitAlignment(4);
|
||||
void *Addr = (void*) (JCE.getCurrentPCValue());
|
||||
if (!sys::Memory::setRangeWritable(Addr, 12))
|
||||
llvm_unreachable("ERROR: Unable to mark stub writable.");
|
||||
|
||||
intptr_t EmittedAddr;
|
||||
if (Fn != (void*)(intptr_t)SparcCompilationCallback)
|
||||
EmittedAddr = (intptr_t)Fn;
|
||||
else
|
||||
EmittedAddr = (intptr_t)SparcCompilationCallback;
|
||||
|
||||
// sethi %hi(EmittedAddr), %g1
|
||||
// jmp %g1+%lo(EmittedAddr), %g1
|
||||
// nop
|
||||
|
||||
JCE.emitWordBE(SETHI_INST(HI(EmittedAddr), 1));
|
||||
JCE.emitWordBE(JMP_INST(1, LO(EmittedAddr), 1));
|
||||
JCE.emitWordBE(NOP_INST);
|
||||
|
||||
sys::Memory::InvalidateInstructionCache(Addr, 12);
|
||||
if (!sys::Memory::setRangeExecutable(Addr, 12))
|
||||
llvm_unreachable("ERROR: Unable to mark stub executable.");
|
||||
|
||||
return Addr;
|
||||
}
|
||||
|
||||
TargetJITInfo::LazyResolverFn
|
||||
SparcJITInfo::getLazyResolverFunction(JITCompilerFn F) {
|
||||
JITCompilerFunction = F;
|
||||
return SparcCompilationCallback;
|
||||
}
|
||||
|
||||
/// relocate - Before the JIT can run a block of code that has been emitted,
|
||||
/// it must rewrite the code to contain the actual addresses of any
|
||||
/// referenced global symbols.
|
||||
void SparcJITInfo::relocate(void *Function, MachineRelocation *MR,
|
||||
unsigned NumRelocs, unsigned char *GOTBase) {
|
||||
for (unsigned i = 0; i != NumRelocs; ++i, ++MR) {
|
||||
void *RelocPos = (char*) Function + MR->getMachineCodeOffset();
|
||||
intptr_t ResultPtr = (intptr_t) MR->getResultPointer();
|
||||
|
||||
switch ((SP::RelocationType) MR->getRelocationType()) {
|
||||
default: llvm_unreachable("Unknown reloc!");
|
||||
case SP::reloc_sparc_hi:
|
||||
ResultPtr = (ResultPtr >> 10) & 0x3fffff;
|
||||
break;
|
||||
|
||||
case SP::reloc_sparc_lo:
|
||||
ResultPtr = (ResultPtr & 0x3ff);
|
||||
break;
|
||||
|
||||
case SP::reloc_sparc_pc30:
|
||||
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffffff;
|
||||
break;
|
||||
|
||||
case SP::reloc_sparc_pc22:
|
||||
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x3fffff;
|
||||
break;
|
||||
|
||||
case SP::reloc_sparc_pc19:
|
||||
ResultPtr = ((ResultPtr - (intptr_t)RelocPos) >> 2) & 0x7ffff;
|
||||
break;
|
||||
}
|
||||
*((unsigned*) RelocPos) |= (unsigned) ResultPtr;
|
||||
}
|
||||
}
|
||||
|
||||
|
67
lib/Target/Sparc/SparcJITInfo.h
Normal file
67
lib/Target/Sparc/SparcJITInfo.h
Normal file
@ -0,0 +1,67 @@
|
||||
//==- SparcJITInfo.h - Sparc Implementation of the JIT Interface -*- C++ -*-==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the declaration of the SparcJITInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCJITINFO_H
|
||||
#define SPARCJITINFO_H
|
||||
|
||||
#include "llvm/CodeGen/MachineConstantPool.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/Target/TargetJITInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
class SparcTargetMachine;
|
||||
|
||||
class SparcJITInfo : public TargetJITInfo {
|
||||
|
||||
bool IsPIC;
|
||||
|
||||
public:
|
||||
explicit SparcJITInfo()
|
||||
: IsPIC(false) {}
|
||||
|
||||
/// replaceMachineCodeForFunction - Make it so that calling the function
|
||||
/// whose machine code is at OLD turns into a call to NEW, perhaps by
|
||||
/// overwriting OLD with a branch to NEW. This is used for self-modifying
|
||||
/// code.
|
||||
///
|
||||
virtual void replaceMachineCodeForFunction(void *Old, void *New);
|
||||
|
||||
// getStubLayout - Returns the size and alignment of the largest call stub
|
||||
// on Sparc.
|
||||
virtual StubLayout getStubLayout();
|
||||
|
||||
|
||||
/// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
|
||||
/// small native function that simply calls the function at the specified
|
||||
/// address.
|
||||
virtual void *emitFunctionStub(const Function *F, void *Fn,
|
||||
JITCodeEmitter &JCE);
|
||||
|
||||
/// getLazyResolverFunction - Expose the lazy resolver to the JIT.
|
||||
virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
|
||||
|
||||
/// relocate - Before the JIT can run a block of code that has been emitted,
|
||||
/// it must rewrite the code to contain the actual addresses of any
|
||||
/// referenced global symbols.
|
||||
virtual void relocate(void *Function, MachineRelocation *MR,
|
||||
unsigned NumRelocs, unsigned char *GOTBase);
|
||||
|
||||
/// Initialize - Initialize internal stage for the function being JITted.
|
||||
void Initialize(const MachineFunction &MF, bool isPIC) {
|
||||
IsPIC = isPIC;
|
||||
}
|
||||
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
41
lib/Target/Sparc/SparcRelocations.h
Normal file
41
lib/Target/Sparc/SparcRelocations.h
Normal file
@ -0,0 +1,41 @@
|
||||
//===-- SparcRelocations.h - Sparc Code Relocations -------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file defines the Sparc target-specific relocation types
|
||||
// (for relocation-model=static).
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARC_RELOCATIONS_H
|
||||
#define SPARC_RELOCATIONS_H
|
||||
|
||||
#include "llvm/CodeGen/MachineRelocation.h"
|
||||
|
||||
namespace llvm {
|
||||
namespace SP {
|
||||
enum RelocationType {
|
||||
// reloc_sparc_hi - upper 22 bits
|
||||
reloc_sparc_hi = 1,
|
||||
|
||||
// reloc_sparc_lo - lower 10 bits
|
||||
reloc_sparc_lo = 2,
|
||||
|
||||
// reloc_sparc_pc30 - pc rel. 30 bits for call
|
||||
reloc_sparc_pc30 = 3,
|
||||
|
||||
// reloc_sparc_pc22 - pc rel. 22 bits for branch
|
||||
reloc_sparc_pc22 = 4,
|
||||
|
||||
// reloc_sparc_pc22 - pc rel. 19 bits for branch with icc/xcc
|
||||
reloc_sparc_pc19 = 5
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
@ -65,6 +65,13 @@ bool SparcPassConfig::addInstSelector() {
|
||||
return false;
|
||||
}
|
||||
|
||||
bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
|
||||
JITCodeEmitter &JCE) {
|
||||
// Machine code emitter pass for Sparc.
|
||||
PM.add(createSparcJITCodeEmitterPass(*this, JCE));
|
||||
return false;
|
||||
}
|
||||
|
||||
/// addPreEmitPass - This pass may be implemented by targets that want to run
|
||||
/// passes immediately before machine code is emitted. This should return
|
||||
/// true if -print-machineinstrs should print out the code after the passes.
|
||||
|
@ -17,6 +17,7 @@
|
||||
#include "SparcFrameLowering.h"
|
||||
#include "SparcISelLowering.h"
|
||||
#include "SparcInstrInfo.h"
|
||||
#include "SparcJITInfo.h"
|
||||
#include "SparcSelectionDAGInfo.h"
|
||||
#include "SparcSubtarget.h"
|
||||
#include "llvm/IR/DataLayout.h"
|
||||
@ -32,6 +33,7 @@ class SparcTargetMachine : public LLVMTargetMachine {
|
||||
SparcTargetLowering TLInfo;
|
||||
SparcSelectionDAGInfo TSInfo;
|
||||
SparcFrameLowering FrameLowering;
|
||||
SparcJITInfo JITInfo;
|
||||
public:
|
||||
SparcTargetMachine(const Target &T, StringRef TT,
|
||||
StringRef CPU, StringRef FS, const TargetOptions &Options,
|
||||
@ -52,10 +54,14 @@ public:
|
||||
virtual const SparcSelectionDAGInfo* getSelectionDAGInfo() const {
|
||||
return &TSInfo;
|
||||
}
|
||||
virtual SparcJITInfo *getJITInfo() {
|
||||
return &JITInfo;
|
||||
}
|
||||
virtual const DataLayout *getDataLayout() const { return &DL; }
|
||||
|
||||
// Pass Pipeline Configuration
|
||||
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
|
||||
virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE);
|
||||
};
|
||||
|
||||
/// SparcV8TargetMachine - Sparc 32-bit target machine
|
||||
|
@ -15,7 +15,9 @@ using namespace llvm;
|
||||
Target llvm::TheSparcTarget;
|
||||
Target llvm::TheSparcV9Target;
|
||||
|
||||
extern "C" void LLVMInitializeSparcTargetInfo() {
|
||||
RegisterTarget<Triple::sparc> X(TheSparcTarget, "sparc", "Sparc");
|
||||
RegisterTarget<Triple::sparcv9> Y(TheSparcV9Target, "sparcv9", "Sparc V9");
|
||||
extern "C" void LLVMInitializeSparcTargetInfo() {
|
||||
RegisterTarget<Triple::sparc, /*HasJIT=*/ true>
|
||||
X(TheSparcTarget, "sparc", "Sparc");
|
||||
RegisterTarget<Triple::sparcv9, /*HasJIT=*/ true>
|
||||
Y(TheSparcV9Target, "sparcv9", "Sparc V9");
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user