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Properly pseudo-ize ARM MOVCCi and MOVCCi16.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127442 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-03-11 01:09:28 +00:00
parent de5e101b0d
commit 3906276a8d
2 changed files with 30 additions and 26 deletions
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21
lib/Target/ARM/ARMExpandPseudoInsts.cpp
View File

@ -735,6 +735,27 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
MI.eraseFromParent();
return true;
}
case ARM::MOVCCi16: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16),
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg());
MI.eraseFromParent();
return true;
}
case ARM::MOVCCi: {
BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi),
MI.getOperand(1).getReg())
.addImm(MI.getOperand(2).getImm())
.addImm(MI.getOperand(3).getImm()) // 'pred'
.addReg(MI.getOperand(4).getReg())
.addReg(0); // 's' bit
MI.eraseFromParent();
return true;
}
case ARM::Int_eh_sjlj_dispatchsetup: {
MachineFunction &MF = *MI.getParent()->getParent();
const ARMBaseInstrInfo *AII =

35
lib/Target/ARM/ARMInstrInfo.td
View File

@ -3163,35 +3163,18 @@ def MOVCCs : ARMPseudoInst<(outs GPR:$Rd),
RegConstraint<"$false = $Rd">;
let isMoveImm = 1 in
def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm_hilo16:$imm),
DPFrm, IIC_iMOVi,
"movw", "\t$Rd, $imm",
[]>,
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>,
UnaryDP {
bits<4> Rd;
bits<16> imm;
let Inst{25} = 1;
let Inst{20} = 0;
let Inst{19-16} = imm{15-12};
let Inst{15-12} = Rd;
let Inst{11-0} = imm{11-0};
}
def MOVCCi16 : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, i32imm_hilo16:$imm, pred:$p),
Size4Bytes, IIC_iMOVi,
[]>,
RegConstraint<"$false = $Rd">, Requires<[IsARM, HasV6T2]>;
let isMoveImm = 1 in
def MOVCCi : AI1<0b1101, (outs GPR:$Rd),
(ins GPR:$false, so_imm:$imm), DPFrm, IIC_iCMOVi,
"mov", "\t$Rd, $imm",
def MOVCCi : ARMPseudoInst<(outs GPR:$Rd),
(ins GPR:$false, so_imm:$imm, pred:$p),
Size4Bytes, IIC_iCMOVi,
[/*(set GPR:$Rd, (ARMcmov GPR:$false, so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">, UnaryDP {
bits<4> Rd;
bits<12> imm;
let Inst{25} = 1;
let Inst{20} = 0;
let Inst{19-16} = 0b0000;
let Inst{15-12} = Rd;
let Inst{11-0} = imm;
}
RegConstraint<"$false = $Rd">;
// Two instruction predicate mov immediate.
let isMoveImm = 1 in