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Add MCInstBuilder, a utility class to simplify MCInst creation similar to MachineInstrBuilder.
Simplify some repetitive code with it. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168587 91177308-0d34-0410-b5e6-96231b3b80d8
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include/llvm/MC/MCInstBuilder.h
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70
include/llvm/MC/MCInstBuilder.h
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@ -0,0 +1,70 @@
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//===-- llvm/MC/MCInstBuilder.h - Simplify creation of MCInsts --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the MCInstBuilder class for convenient creation of
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// MCInsts.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_MC_MCINSTBUILDER_H
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#define LLVM_MC_MCINSTBUILDER_H
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCStreamer.h"
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namespace llvm {
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class MCInstBuilder {
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MCInst Inst;
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public:
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/// \brief Create a new MCInstBuilder for an MCInst with a specific opcode.
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MCInstBuilder(unsigned Opcode) {
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Inst.setOpcode(Opcode);
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}
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/// \brief Add a new register operand.
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MCInstBuilder &addReg(unsigned Reg) {
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Inst.addOperand(MCOperand::CreateReg(Reg));
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return *this;
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}
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/// \brief Add a new integer immediate operand.
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MCInstBuilder &addImm(int64_t Val) {
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Inst.addOperand(MCOperand::CreateImm(Val));
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return *this;
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}
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/// \brief Add a new floating point immediate operand.
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MCInstBuilder &addFPImm(double Val) {
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Inst.addOperand(MCOperand::CreateFPImm(Val));
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return *this;
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}
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/// \brief Add a new MCExpr operand.
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MCInstBuilder &addExpr(const MCExpr *Val) {
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Inst.addOperand(MCOperand::CreateExpr(Val));
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return *this;
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}
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/// \brief Add a new MCInst operand.
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MCInstBuilder &addInst(const MCInst *Val) {
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Inst.addOperand(MCOperand::CreateInst(Val));
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return *this;
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}
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/// \brief Emit the built instruction to an MCStreamer.
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void emit(MCStreamer &OutStreamer) {
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OutStreamer.EmitInstruction(Inst);
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}
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};
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} // end namespace llvm
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#endif
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@ -37,6 +37,7 @@
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCObjectStreamer.h"
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#include "llvm/MC/MCStreamer.h"
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@ -1051,12 +1052,11 @@ void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
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OutContext);
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// If this isn't a TBB or TBH, the entries are direct branch instructions.
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if (OffsetWidth == 4) {
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MCInst BrInst;
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BrInst.setOpcode(ARM::t2B);
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BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr));
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BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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BrInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(BrInst);
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MCInstBuilder(ARM::t2B)
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.addExpr(MBBSymbolExpr)
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.addImm(ARMCC::AL)
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.addReg(0)
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.emit(OutStreamer);
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continue;
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}
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// Otherwise it's an offset from the dispatch instruction. Construct an
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@ -1100,18 +1100,6 @@ void ARMAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
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printOperand(MI, NOps-2, OS);
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}
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static void populateADROperands(MCInst &Inst, unsigned Dest,
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const MCSymbol *Label,
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unsigned pred, unsigned ccreg,
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MCContext &Ctx) {
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const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, Ctx);
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Inst.addOperand(MCOperand::CreateReg(Dest));
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Inst.addOperand(MCOperand::CreateExpr(SymbolExpr));
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// Add predicate operands.
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Inst.addOperand(MCOperand::CreateImm(pred));
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Inst.addOperand(MCOperand::CreateReg(ccreg));
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}
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void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
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assert(MI->getFlag(MachineInstr::FrameSetup) &&
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"Only instruction which are involved into frame setup code are allowed");
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@ -1288,129 +1276,112 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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case ARM::tLEApcrel:
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case ARM::t2LEApcrel: {
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// FIXME: Need to also handle globals and externals
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MCInst TmpInst;
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TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
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: (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
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: ARM::ADR));
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populateADROperands(TmpInst, MI->getOperand(0).getReg(),
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GetCPISymbol(MI->getOperand(1).getIndex()),
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MI->getOperand(2).getImm(), MI->getOperand(3).getReg(),
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OutContext);
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OutStreamer.EmitInstruction(TmpInst);
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MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
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MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrel ? ARM::t2ADR
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: (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
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: ARM::ADR))
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.addReg(MI->getOperand(0).getReg())
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.addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
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// Add predicate operands.
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.addImm(MI->getOperand(2).getImm())
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.addReg(MI->getOperand(3).getReg())
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.emit(OutStreamer);
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return;
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}
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case ARM::LEApcrelJT:
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case ARM::tLEApcrelJT:
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case ARM::t2LEApcrelJT: {
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MCInst TmpInst;
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TmpInst.setOpcode(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
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: (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
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: ARM::ADR));
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populateADROperands(TmpInst, MI->getOperand(0).getReg(),
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GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
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MI->getOperand(2).getImm()),
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MI->getOperand(3).getImm(), MI->getOperand(4).getReg(),
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OutContext);
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OutStreamer.EmitInstruction(TmpInst);
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MCSymbol *JTIPICSymbol =
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GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
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MI->getOperand(2).getImm());
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MCInstBuilder(MI->getOpcode() == ARM::t2LEApcrelJT ? ARM::t2ADR
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: (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
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: ARM::ADR))
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.addReg(MI->getOperand(0).getReg())
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.addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
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// Add predicate operands.
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.addImm(MI->getOperand(3).getImm())
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.addReg(MI->getOperand(4).getReg())
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.emit(OutStreamer);
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return;
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}
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// Darwin call instructions are just normal call instructions with different
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// clobber semantics (they clobber R9).
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case ARM::BX_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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MCInstBuilder(ARM::MOVr)
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.addReg(ARM::LR)
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.addReg(ARM::PC)
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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.addImm(ARMCC::AL)
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.addReg(0)
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::BX);
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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OutStreamer.EmitInstruction(TmpInst);
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}
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.addReg(0)
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.emit(OutStreamer);
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MCInstBuilder(ARM::BX)
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.addReg(MI->getOperand(0).getReg())
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.emit(OutStreamer);
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return;
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}
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case ARM::tBX_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tMOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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MCInstBuilder(ARM::tMOVr)
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.addReg(ARM::LR)
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.addReg(ARM::PC)
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tBX);
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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.addImm(ARMCC::AL)
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.addReg(0)
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.emit(OutStreamer);
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MCInstBuilder(ARM::tBX)
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.addReg(MI->getOperand(0).getReg())
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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.addImm(ARMCC::AL)
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.addReg(0)
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.emit(OutStreamer);
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return;
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}
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case ARM::BMOVPCRX_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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MCInstBuilder(ARM::MOVr)
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.addReg(ARM::LR)
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.addReg(ARM::PC)
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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.addImm(ARMCC::AL)
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.addReg(0)
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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.addReg(0)
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.emit(OutStreamer);
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MCInstBuilder(ARM::MOVr)
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.addReg(ARM::PC)
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.addImm(MI->getOperand(0).getReg())
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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.addImm(ARMCC::AL)
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.addReg(0)
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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.addReg(0)
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.emit(OutStreamer);
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return;
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}
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case ARM::BMOVPCB_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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MCInstBuilder(ARM::MOVr)
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.addReg(ARM::LR)
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.addReg(ARM::PC)
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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.addImm(ARMCC::AL)
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.addReg(0)
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::Bcc);
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const GlobalValue *GV = MI->getOperand(0).getGlobal();
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MCSymbol *GVSym = Mang->getSymbol(GV);
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const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
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TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
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.addReg(0)
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.emit(OutStreamer);
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const GlobalValue *GV = MI->getOperand(0).getGlobal();
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MCSymbol *GVSym = Mang->getSymbol(GV);
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const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
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MCInstBuilder(ARM::Bcc)
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.addExpr(GVSymExpr)
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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.addImm(ARMCC::AL)
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.addReg(0)
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.emit(OutStreamer);
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return;
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}
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case ARM::MOVi16_ga_pcrel:
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@ -1498,15 +1469,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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OutContext));
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// Form and emit the add.
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MCInst AddInst;
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AddInst.setOpcode(ARM::tADDhirr);
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
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// Add predicate operands.
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AddInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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AddInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(AddInst);
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MCInstBuilder(ARM::tADDhirr)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(0).getReg())
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.addReg(ARM::PC)
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// Add predicate operands.
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.addImm(ARMCC::AL)
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.addReg(0)
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.emit(OutStreamer);
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return;
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}
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case ARM::PICADD: {
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@ -1521,17 +1491,16 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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OutContext));
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// Form and emit the add.
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MCInst AddInst;
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AddInst.setOpcode(ARM::ADDrr);
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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// Add predicate operands.
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AddInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
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AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
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// Add 's' bit operand (always reg0 for this)
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AddInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(AddInst);
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MCInstBuilder(ARM::ADDrr)
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.addReg(MI->getOperand(0).getReg())
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.addReg(ARM::PC)
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.addReg(MI->getOperand(1).getReg())
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// Add predicate operands.
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.addImm(MI->getOperand(3).getImm())
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.addReg(MI->getOperand(4).getReg())
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// Add 's' bit operand (always reg0 for this)
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.addReg(0)
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.emit(OutStreamer);
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return;
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}
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case ARM::PICSTR:
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@ -1567,16 +1536,15 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
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case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
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}
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MCInst LdStInst;
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LdStInst.setOpcode(Opcode);
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LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
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LdStInst.addOperand(MCOperand::CreateReg(ARM::PC));
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LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
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LdStInst.addOperand(MCOperand::CreateImm(0));
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// Add predicate operands.
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LdStInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
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LdStInst.addOperand(MCOperand::CreateReg(MI->getOperand(4).getReg()));
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OutStreamer.EmitInstruction(LdStInst);
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MCInstBuilder(Opcode)
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.addReg(MI->getOperand(0).getReg())
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.addReg(ARM::PC)
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.addReg(MI->getOperand(1).getReg())
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.addImm(0)
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// Add predicate operands.
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.addImm(MI->getOperand(3).getImm())
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.addReg(MI->getOperand(4).getReg())
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.emit(OutStreamer);
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return;
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}
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@ -1606,29 +1574,28 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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case ARM::t2BR_JT: {
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// Lower and emit the instruction itself, then the jump table following it.
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MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tMOVr);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
// Add predicate operands.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(ARM::tMOVr)
|
||||
.addReg(ARM::PC)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
// Add predicate operands.
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
// Output the data for the jump table itself
|
||||
EmitJump2Table(MI);
|
||||
return;
|
||||
}
|
||||
case ARM::t2TBB_JT: {
|
||||
// Lower and emit the instruction itself, then the jump table following it.
|
||||
MCInst TmpInst;
|
||||
MCInstBuilder(ARM::t2TBB)
|
||||
.addReg(ARM::PC)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
// Add predicate operands.
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
TmpInst.setOpcode(ARM::t2TBB);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
// Add predicate operands.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
// Output the data for the jump table itself
|
||||
EmitJump2Table(MI);
|
||||
// Make sure the next instruction is 2-byte aligned.
|
||||
@ -1637,15 +1604,14 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
}
|
||||
case ARM::t2TBH_JT: {
|
||||
// Lower and emit the instruction itself, then the jump table following it.
|
||||
MCInst TmpInst;
|
||||
MCInstBuilder(ARM::t2TBH)
|
||||
.addReg(ARM::PC)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
// Add predicate operands.
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
TmpInst.setOpcode(ARM::t2TBH);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
// Add predicate operands.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
// Output the data for the jump table itself
|
||||
EmitJump2Table(MI);
|
||||
return;
|
||||
@ -1705,17 +1671,16 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
case ARM::BR_JTadd: {
|
||||
// Lower and emit the instruction itself, then the jump table following it.
|
||||
// add pc, target, idx
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::ADDrr);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
||||
// Add predicate operands.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
// Add 's' bit operand (always reg0 for this)
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(ARM::ADDrr)
|
||||
.addReg(ARM::PC)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(1).getReg())
|
||||
// Add predicate operands.
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
// Add 's' bit operand (always reg0 for this)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
// Output the data for the jump table itself
|
||||
EmitJumpTable(MI);
|
||||
@ -1759,75 +1724,63 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
unsigned SrcReg = MI->getOperand(0).getReg();
|
||||
unsigned ValReg = MI->getOperand(1).getReg();
|
||||
MCSymbol *Label = GetARMSJLJEHLabel();
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tMOVr);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
OutStreamer.AddComment("eh_setjmp begin");
|
||||
MCInstBuilder(ARM::tMOVr)
|
||||
.addReg(ValReg)
|
||||
.addReg(ARM::PC)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.AddComment("eh_setjmp begin");
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tADDi3);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tADDi3)
|
||||
.addReg(ValReg)
|
||||
// 's' bit operand
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(7));
|
||||
.addReg(ARM::CPSR)
|
||||
.addReg(ValReg)
|
||||
.addImm(7)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tSTRi);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tSTRi)
|
||||
.addReg(ValReg)
|
||||
.addReg(SrcReg)
|
||||
// The offset immediate is #4. The operand value is scaled by 4 for the
|
||||
// tSTR instruction.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(1));
|
||||
.addImm(1)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tMOVi8);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tMOVi8)
|
||||
.addReg(ARM::R0)
|
||||
.addReg(ARM::CPSR)
|
||||
.addImm(0)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tB);
|
||||
TmpInst.addOperand(MCOperand::CreateExpr(SymbolExpr));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tMOVi8);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(1));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
|
||||
MCInstBuilder(ARM::tB)
|
||||
.addExpr(SymbolExpr)
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
OutStreamer.AddComment("eh_setjmp end");
|
||||
MCInstBuilder(ARM::tMOVi8)
|
||||
.addReg(ARM::R0)
|
||||
.addReg(ARM::CPSR)
|
||||
.addImm(1)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.AddComment("eh_setjmp end");
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
OutStreamer.EmitLabel(Label);
|
||||
return;
|
||||
}
|
||||
@ -1843,69 +1796,58 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
unsigned SrcReg = MI->getOperand(0).getReg();
|
||||
unsigned ValReg = MI->getOperand(1).getReg();
|
||||
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::ADDri);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(8));
|
||||
OutStreamer.AddComment("eh_setjmp begin");
|
||||
MCInstBuilder(ARM::ADDri)
|
||||
.addReg(ValReg)
|
||||
.addReg(ARM::PC)
|
||||
.addImm(8)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
// 's' bit operand (always reg0 for this).
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.AddComment("eh_setjmp begin");
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::STRi12);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ValReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(4));
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::STRi12)
|
||||
.addReg(ValReg)
|
||||
.addReg(SrcReg)
|
||||
.addImm(4)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::MOVi);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::MOVi)
|
||||
.addReg(ARM::R0)
|
||||
.addImm(0)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
// 's' bit operand (always reg0 for this).
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::ADDri);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(0));
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::ADDri)
|
||||
.addReg(ARM::PC)
|
||||
.addReg(ARM::PC)
|
||||
.addImm(0)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
// 's' bit operand (always reg0 for this).
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::MOVi);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::R0));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(1));
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
OutStreamer.AddComment("eh_setjmp end");
|
||||
MCInstBuilder(ARM::MOVi)
|
||||
.addReg(ARM::R0)
|
||||
.addImm(1)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
// 's' bit operand (always reg0 for this).
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.AddComment("eh_setjmp end");
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
return;
|
||||
}
|
||||
case ARM::Int_eh_sjlj_longjmp: {
|
||||
@ -1915,48 +1857,39 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
// bx $scratch
|
||||
unsigned SrcReg = MI->getOperand(0).getReg();
|
||||
unsigned ScratchReg = MI->getOperand(1).getReg();
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::LDRi12);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(8));
|
||||
MCInstBuilder(ARM::LDRi12)
|
||||
.addReg(ARM::SP)
|
||||
.addReg(SrcReg)
|
||||
.addImm(8)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::LDRi12);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(4));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::LDRi12)
|
||||
.addReg(ScratchReg)
|
||||
.addReg(SrcReg)
|
||||
.addImm(4)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::LDRi12);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::LDRi12)
|
||||
.addReg(ARM::R7)
|
||||
.addReg(SrcReg)
|
||||
.addImm(0)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::BX);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::BX)
|
||||
.addReg(ScratchReg)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
return;
|
||||
}
|
||||
case ARM::tInt_eh_sjlj_longjmp: {
|
||||
@ -1967,60 +1900,49 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
// bx $scratch
|
||||
unsigned SrcReg = MI->getOperand(0).getReg();
|
||||
unsigned ScratchReg = MI->getOperand(1).getReg();
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tLDRi);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
MCInstBuilder(ARM::tLDRi)
|
||||
.addReg(ScratchReg)
|
||||
.addReg(SrcReg)
|
||||
// The offset immediate is #8. The operand value is scaled by 4 for the
|
||||
// tLDR instruction.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(2));
|
||||
.addImm(2)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tMOVr);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tMOVr)
|
||||
.addReg(ARM::SP)
|
||||
.addReg(ScratchReg)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tLDRi);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(1));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tLDRi)
|
||||
.addReg(ScratchReg)
|
||||
.addReg(SrcReg)
|
||||
.addImm(1)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tLDRi);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ARM::R7));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(SrcReg));
|
||||
TmpInst.addOperand(MCOperand::CreateImm(0));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tLDRi)
|
||||
.addReg(ARM::R7)
|
||||
.addReg(SrcReg)
|
||||
.addImm(0)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
{
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(ARM::tBX);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCInstBuilder(ARM::tBX)
|
||||
.addReg(ScratchReg)
|
||||
// Predicate.
|
||||
TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(0));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
.addImm(ARMCC::AL)
|
||||
.addReg(0)
|
||||
.emit(OutStreamer);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
@ -37,6 +37,7 @@
|
||||
#include "llvm/MC/MCContext.h"
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCInstBuilder.h"
|
||||
#include "llvm/MC/MCSectionMachO.h"
|
||||
#include "llvm/MC/MCStreamer.h"
|
||||
#include "llvm/MC/MCSymbol.h"
|
||||
@ -55,7 +56,6 @@
|
||||
#include "llvm/ADT/StringExtras.h"
|
||||
#include "llvm/ADT/SmallString.h"
|
||||
#include "llvm/ADT/MapVector.h"
|
||||
#include "llvm/ADT/VariadicFunction.h"
|
||||
using namespace llvm;
|
||||
|
||||
namespace {
|
||||
@ -350,14 +350,11 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
MCSymbol *PICBase = MF->getPICBaseSymbol();
|
||||
|
||||
// Emit the 'bl'.
|
||||
TmpInst.setOpcode(PPC::BL_Darwin); // Darwin vs SVR4 doesn't matter here.
|
||||
|
||||
|
||||
// FIXME: We would like an efficient form for this, so we don't have to do
|
||||
// a lot of extra uniquing.
|
||||
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::
|
||||
Create(PICBase, OutContext)));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(PPC::BL_Darwin) // Darwin vs SVR4 doesn't matter here.
|
||||
// FIXME: We would like an efficient form for this, so we don't have to do
|
||||
// a lot of extra uniquing.
|
||||
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))
|
||||
.emit(OutStreamer);
|
||||
|
||||
// Emit the label.
|
||||
OutStreamer.EmitLabel(PICBase);
|
||||
@ -406,9 +403,9 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
// Into: %R3 = MFCR ;; cr7
|
||||
OutStreamer.AddComment(PPCInstPrinter::
|
||||
getRegisterName(MI->getOperand(1).getReg()));
|
||||
TmpInst.setOpcode(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
.emit(OutStreamer);
|
||||
return;
|
||||
case PPC::SYNC:
|
||||
// In Book E sync is called msync, handle this special case here...
|
||||
@ -559,21 +556,6 @@ static MCSymbol *GetAnonSym(MCSymbol *Sym, MCContext &Ctx) {
|
||||
return Ctx.GetOrCreateSymbol(Sym->getName() + "$tmp");
|
||||
}
|
||||
|
||||
namespace {
|
||||
// Helper function to emit a custom MCInst.
|
||||
void emitMCInstImpl(MCStreamer &OutStreamer, unsigned Opcode,
|
||||
ArrayRef<const MCOperand *> Ops) {
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(Opcode);
|
||||
for (unsigned I = 0, E = Ops.size(); I != E; ++I)
|
||||
TmpInst.addOperand(*Ops[I]);
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
}
|
||||
|
||||
const VariadicFunction2<void, MCStreamer &, unsigned, MCOperand,
|
||||
emitMCInstImpl> emitMCInst = {};
|
||||
}
|
||||
|
||||
void PPCDarwinAsmPrinter::
|
||||
EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
|
||||
bool isPPC64 = TM.getDataLayout()->getPointerSizeInBits() == 64;
|
||||
@ -604,36 +586,36 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
|
||||
OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol);
|
||||
|
||||
// mflr r0
|
||||
emitMCInst(OutStreamer, PPC::MFLR, MCOperand::CreateReg(PPC::R0));
|
||||
MCInstBuilder(PPC::MFLR).addReg(PPC::R0).emit(OutStreamer);
|
||||
// FIXME: MCize this.
|
||||
OutStreamer.EmitRawText("\tbcl 20, 31, " + Twine(AnonSymbol->getName()));
|
||||
OutStreamer.EmitLabel(AnonSymbol);
|
||||
// mflr r11
|
||||
emitMCInst(OutStreamer, PPC::MFLR, MCOperand::CreateReg(PPC::R11));
|
||||
MCInstBuilder(PPC::MFLR).addReg(PPC::R11).emit(OutStreamer);
|
||||
// addis r11, r11, ha16(LazyPtr - AnonSymbol)
|
||||
MCOperand Sub = MCOperand::CreateExpr(
|
||||
MCBinaryExpr::CreateSub(
|
||||
MCSymbolRefExpr::Create(LazyPtr, OutContext),
|
||||
MCSymbolRefExpr::Create(AnonSymbol, OutContext),
|
||||
OutContext));
|
||||
emitMCInst(OutStreamer, PPC::ADDIS, MCOperand::CreateReg(PPC::R11),
|
||||
MCOperand::CreateReg(PPC::R11), Sub);
|
||||
const MCExpr *Sub =
|
||||
MCBinaryExpr::CreateSub(MCSymbolRefExpr::Create(LazyPtr, OutContext),
|
||||
MCSymbolRefExpr::Create(AnonSymbol, OutContext),
|
||||
OutContext);
|
||||
MCInstBuilder(PPC::ADDIS)
|
||||
.addReg(PPC::R11)
|
||||
.addReg(PPC::R11)
|
||||
.addExpr(Sub)
|
||||
.emit(OutStreamer);
|
||||
// mtlr r0
|
||||
emitMCInst(OutStreamer, PPC::MTLR, MCOperand::CreateReg(PPC::R0));
|
||||
MCInstBuilder(PPC::MTLR).addReg(PPC::R0).emit(OutStreamer);
|
||||
|
||||
if (isPPC64) {
|
||||
// ldu r12, lo16(LazyPtr - AnonSymbol)(r11)
|
||||
emitMCInst(OutStreamer, PPC::LDU, MCOperand::CreateReg(PPC::R12),
|
||||
Sub, Sub, MCOperand::CreateReg(PPC::R11));
|
||||
} else {
|
||||
// lwzu r12, lo16(LazyPtr - AnonSymbol)(r11)
|
||||
emitMCInst(OutStreamer, PPC::LWZU, MCOperand::CreateReg(PPC::R12),
|
||||
Sub, Sub, MCOperand::CreateReg(PPC::R11));
|
||||
}
|
||||
// ldu r12, lo16(LazyPtr - AnonSymbol)(r11)
|
||||
// lwzu r12, lo16(LazyPtr - AnonSymbol)(r11)
|
||||
MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
|
||||
.addReg(PPC::R12)
|
||||
.addExpr(Sub).addExpr(Sub)
|
||||
.addReg(PPC::R11)
|
||||
.emit(OutStreamer);
|
||||
// mtctr r12
|
||||
emitMCInst(OutStreamer, PPC::MTCTR, MCOperand::CreateReg(PPC::R12));
|
||||
MCInstBuilder(PPC::MTCTR).addReg(PPC::R12).emit(OutStreamer);
|
||||
// bctr
|
||||
emitMCInst(OutStreamer, PPC::BCTR);
|
||||
MCInstBuilder(PPC::BCTR).emit(OutStreamer);
|
||||
|
||||
OutStreamer.SwitchSection(LSPSection);
|
||||
OutStreamer.EmitLabel(LazyPtr);
|
||||
@ -668,30 +650,30 @@ EmitFunctionStubs(const MachineModuleInfoMachO::SymbolListTy &Stubs) {
|
||||
OutStreamer.EmitLabel(Stub);
|
||||
OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol);
|
||||
// lis r11, ha16(LazyPtr)
|
||||
MCOperand LazyPtrHa16 =
|
||||
MCOperand::CreateExpr(
|
||||
MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_HA16,
|
||||
OutContext));
|
||||
emitMCInst(OutStreamer, PPC::LIS, MCOperand::CreateReg(PPC::R11),
|
||||
LazyPtrHa16);
|
||||
const MCExpr *LazyPtrHa16 =
|
||||
MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_HA16,
|
||||
OutContext);
|
||||
MCInstBuilder(PPC::LIS)
|
||||
.addReg(PPC::R11)
|
||||
.addExpr(LazyPtrHa16)
|
||||
.emit(OutStreamer);
|
||||
|
||||
const MCExpr *LazyPtrLo16 =
|
||||
MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_LO16,
|
||||
OutContext);
|
||||
// ldu r12, lo16(LazyPtr)(r11)
|
||||
// lwzu r12, lo16(LazyPtr)(r11)
|
||||
MCInstBuilder(isPPC64 ? PPC::LDU : PPC::LWZU)
|
||||
.addReg(PPC::R12)
|
||||
.addExpr(LazyPtrLo16).addExpr(LazyPtrLo16)
|
||||
.addReg(PPC::R11)
|
||||
.emit(OutStreamer);
|
||||
|
||||
MCOperand LazyPtrLo16 =
|
||||
MCOperand::CreateExpr(
|
||||
MCSymbolRefExpr::Create(LazyPtr, MCSymbolRefExpr::VK_PPC_DARWIN_LO16,
|
||||
OutContext));
|
||||
if (isPPC64) {
|
||||
// ldu r12, lo16(LazyPtr)(r11)
|
||||
emitMCInst(OutStreamer, PPC::LDU, MCOperand::CreateReg(PPC::R12),
|
||||
LazyPtrLo16, LazyPtrLo16, MCOperand::CreateReg(PPC::R11));
|
||||
} else {
|
||||
// lwzu r12, lo16(LazyPtr)(r11)
|
||||
emitMCInst(OutStreamer, PPC::LWZU, MCOperand::CreateReg(PPC::R12),
|
||||
LazyPtrLo16, LazyPtrLo16, MCOperand::CreateReg(PPC::R11));
|
||||
}
|
||||
// mtctr r12
|
||||
emitMCInst(OutStreamer, PPC::MTCTR, MCOperand::CreateReg(PPC::R12));
|
||||
MCInstBuilder(PPC::MTCTR).addReg(PPC::R12).emit(OutStreamer);
|
||||
// bctr
|
||||
emitMCInst(OutStreamer, PPC::BCTR);
|
||||
MCInstBuilder(PPC::BCTR).emit(OutStreamer);
|
||||
|
||||
OutStreamer.SwitchSection(LSPSection);
|
||||
OutStreamer.EmitLabel(LazyPtr);
|
||||
OutStreamer.EmitSymbolAttribute(RawSym, MCSA_IndirectSymbol);
|
||||
|
@ -21,6 +21,7 @@
|
||||
#include "llvm/MC/MCContext.h"
|
||||
#include "llvm/MC/MCExpr.h"
|
||||
#include "llvm/MC/MCInst.h"
|
||||
#include "llvm/MC/MCInstBuilder.h"
|
||||
#include "llvm/MC/MCStreamer.h"
|
||||
#include "llvm/MC/MCSymbol.h"
|
||||
#include "llvm/Target/Mangler.h"
|
||||
@ -549,18 +550,14 @@ ReSimplify:
|
||||
OutMI.setOpcode(X86::RET);
|
||||
break;
|
||||
|
||||
case X86::MORESTACK_RET_RESTORE_R10: {
|
||||
MCInst retInst;
|
||||
|
||||
case X86::MORESTACK_RET_RESTORE_R10:
|
||||
OutMI.setOpcode(X86::MOV64rr);
|
||||
OutMI.addOperand(MCOperand::CreateReg(X86::R10));
|
||||
OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
|
||||
|
||||
retInst.setOpcode(X86::RET);
|
||||
AsmPrinter.OutStreamer.EmitInstruction(retInst);
|
||||
MCInstBuilder(X86::RET).emit(AsmPrinter.OutStreamer);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void LowerTlsAddr(MCStreamer &OutStreamer,
|
||||
@ -574,11 +571,8 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
|
||||
|
||||
MCContext &context = OutStreamer.getContext();
|
||||
|
||||
if (needsPadding) {
|
||||
MCInst prefix;
|
||||
prefix.setOpcode(X86::DATA16_PREFIX);
|
||||
OutStreamer.EmitInstruction(prefix);
|
||||
}
|
||||
if (needsPadding)
|
||||
MCInstBuilder(X86::DATA16_PREFIX).emit(OutStreamer);
|
||||
|
||||
MCSymbolRefExpr::VariantKind SRVK;
|
||||
switch (MI.getOpcode()) {
|
||||
@ -628,20 +622,11 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
|
||||
OutStreamer.EmitInstruction(LEA);
|
||||
|
||||
if (needsPadding) {
|
||||
MCInst prefix;
|
||||
prefix.setOpcode(X86::DATA16_PREFIX);
|
||||
OutStreamer.EmitInstruction(prefix);
|
||||
prefix.setOpcode(X86::DATA16_PREFIX);
|
||||
OutStreamer.EmitInstruction(prefix);
|
||||
prefix.setOpcode(X86::REX64_PREFIX);
|
||||
OutStreamer.EmitInstruction(prefix);
|
||||
MCInstBuilder(X86::DATA16_PREFIX).emit(OutStreamer);
|
||||
MCInstBuilder(X86::DATA16_PREFIX).emit(OutStreamer);
|
||||
MCInstBuilder(X86::REX64_PREFIX).emit(OutStreamer);
|
||||
}
|
||||
|
||||
MCInst call;
|
||||
if (is64Bits)
|
||||
call.setOpcode(X86::CALL64pcrel32);
|
||||
else
|
||||
call.setOpcode(X86::CALLpcrel32);
|
||||
StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
|
||||
MCSymbol *tlsGetAddr = context.GetOrCreateSymbol(name);
|
||||
const MCSymbolRefExpr *tlsRef =
|
||||
@ -649,8 +634,9 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
|
||||
MCSymbolRefExpr::VK_PLT,
|
||||
context);
|
||||
|
||||
call.addOperand(MCOperand::CreateExpr(tlsRef));
|
||||
OutStreamer.EmitInstruction(call);
|
||||
MCInstBuilder(is64Bits ? X86::CALL64pcrel32 : X86::CALLpcrel32)
|
||||
.addExpr(tlsRef)
|
||||
.emit(OutStreamer);
|
||||
}
|
||||
|
||||
void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
@ -694,7 +680,6 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
return LowerTlsAddr(OutStreamer, MCInstLowering, *MI);
|
||||
|
||||
case X86::MOVPC32r: {
|
||||
MCInst TmpInst;
|
||||
// This is a pseudo op for a two instruction sequence with a label, which
|
||||
// looks like:
|
||||
// call "L1$pb"
|
||||
@ -703,20 +688,19 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
|
||||
// Emit the call.
|
||||
MCSymbol *PICBase = MF->getPICBaseSymbol();
|
||||
TmpInst.setOpcode(X86::CALLpcrel32);
|
||||
// FIXME: We would like an efficient form for this, so we don't have to do a
|
||||
// lot of extra uniquing.
|
||||
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
|
||||
OutContext)));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(X86::CALLpcrel32)
|
||||
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext))
|
||||
.emit(OutStreamer);
|
||||
|
||||
// Emit the label.
|
||||
OutStreamer.EmitLabel(PICBase);
|
||||
|
||||
// popl $reg
|
||||
TmpInst.setOpcode(X86::POP32r);
|
||||
TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(X86::POP32r)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
.emit(OutStreamer);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -746,12 +730,11 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
|
||||
DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
|
||||
DotExpr, OutContext);
|
||||
|
||||
MCInst TmpInst;
|
||||
TmpInst.setOpcode(X86::ADD32ri);
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
|
||||
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
|
||||
TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
|
||||
OutStreamer.EmitInstruction(TmpInst);
|
||||
MCInstBuilder(X86::ADD32ri)
|
||||
.addReg(MI->getOperand(0).getReg())
|
||||
.addReg(MI->getOperand(1).getReg())
|
||||
.addExpr(DotExpr)
|
||||
.emit(OutStreamer);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
Loading…
Reference in New Issue
Block a user