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https://github.com/c64scene-ar/llvm-6502.git
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[SKX] Enabling mask instructions: encoding, lowering
KMOVB, KMOVW, KMOVD, KMOVQ, KNOTB, KNOTW, KNOTD, KNOTQ Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
parent
afb1938c39
commit
3922da8ae8
@ -1505,6 +1505,11 @@ void X86TargetLowering::resetOperationActions() {
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}
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}// has AVX-512
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if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {
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addRegisterClass(MVT::v32i1, &X86::VK32RegClass);
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addRegisterClass(MVT::v64i1, &X86::VK64RegClass);
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}
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// SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion
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// of this type with custom code.
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for (int VT = MVT::FIRST_VECTOR_VALUETYPE;
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@ -2312,6 +2317,10 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
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RC = &X86::VK8RegClass;
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else if (RegVT == MVT::v16i1)
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RC = &X86::VK16RegClass;
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else if (RegVT == MVT::v32i1)
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RC = &X86::VK32RegClass;
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else if (RegVT == MVT::v64i1)
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RC = &X86::VK64RegClass;
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else
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llvm_unreachable("Unknown argument type!");
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@ -1031,14 +1031,14 @@ def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
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//
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multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
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string OpcodeStr, RegisterClass KRC,
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ValueType vt, X86MemOperand x86memop> {
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ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
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let hasSideEffects = 0 in {
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def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
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let mayLoad = 1 in
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def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
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[(set KRC:$dst, (vt (load addr:$src)))]>;
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[(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
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let mayStore = 1 in
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def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
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@ -1056,33 +1056,79 @@ multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
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}
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}
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let Predicates = [HasAVX512] in {
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defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16mem>,
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VEX, PS;
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defm KMOVW : avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
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let Predicates = [HasDQI] in
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defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
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i8mem>,
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avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
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VEX, PD;
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let Predicates = [HasAVX512] in
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defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
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i16mem>,
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avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
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VEX, PS;
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let Predicates = [HasBWI] in {
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defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
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i32mem>, VEX, PD, VEX_W;
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defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
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VEX, XD;
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}
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let Predicates = [HasBWI] in {
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defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
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i64mem>, VEX, PS, VEX_W;
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defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
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VEX, XD, VEX_W;
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}
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// GR from/to mask register
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let Predicates = [HasDQI] in {
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def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
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(KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
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def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
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(EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
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}
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let Predicates = [HasAVX512] in {
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// GR16 from/to 16-bit mask
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def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
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(KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
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def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
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(EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
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def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
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def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
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}
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// Store kreg in memory
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def : Pat<(store (v16i1 VK16:$src), addr:$dst),
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// Load/store kreg
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let Predicates = [HasDQI] in {
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def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
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(KMOVBmk addr:$dst, VK8:$src)>;
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
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(KMOVWmk addr:$dst, VK16:$src)>;
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def : Pat<(store VK8:$src, addr:$dst),
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def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
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(KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
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def : Pat<(i1 (load addr:$src)),
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(COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
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def : Pat<(v8i1 (load addr:$src)),
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def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
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(COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
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(KMOVDmk addr:$dst, VK32:$src)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
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(KMOVQmk addr:$dst, VK64:$src)>;
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}
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let Predicates = [HasAVX512] in {
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def : Pat<(i1 (trunc (i32 GR32:$src))),
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(COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
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@ -1094,7 +1140,7 @@ let Predicates = [HasAVX512] in {
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(COPY_TO_REGCLASS
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(KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
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VK1)>;
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def : Pat<(i32 (zext VK1:$src)),
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(AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
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def : Pat<(i8 (zext VK1:$src)),
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@ -1113,6 +1159,14 @@ let Predicates = [HasAVX512] in {
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def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
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(COPY_TO_REGCLASS VK1:$src, VK8)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
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(COPY_TO_REGCLASS VK1:$src, VK32)>;
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def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
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(COPY_TO_REGCLASS VK1:$src, VK64)>;
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}
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// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
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let Predicates = [HasAVX512] in {
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// GR from/to 8-bit mask without native support
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@ -1129,26 +1183,38 @@ let Predicates = [HasAVX512] in {
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(COPY_TO_REGCLASS VK16:$src, VK1)>;
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def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK8:$src, VK1)>;
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}
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let Predicates = [HasBWI] in {
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def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK32:$src, VK1)>;
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def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
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(COPY_TO_REGCLASS VK64:$src, VK1)>;
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}
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// Mask unary operation
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// - KNOT
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multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
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RegisterClass KRC, SDPatternOperator OpNode> {
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let Predicates = [HasAVX512] in
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RegisterClass KRC, SDPatternOperator OpNode,
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Predicate prd> {
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let Predicates = [prd] in
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def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
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!strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
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[(set KRC:$dst, (OpNode KRC:$src))]>;
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}
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multiclass avx512_mask_unop_w<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode> {
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defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
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VEX, PS;
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multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
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SDPatternOperator OpNode> {
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defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
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HasDQI>, VEX, PD;
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defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
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HasAVX512>, VEX, PS;
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defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
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HasBWI>, VEX, PD, VEX_W;
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defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
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HasBWI>, VEX, PS, VEX_W;
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}
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defm KNOT : avx512_mask_unop_w<0x44, "knot", not>;
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defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
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multiclass avx512_mask_unop_int<string IntName, string InstName> {
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let Predicates = [HasAVX512] in
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@ -1159,14 +1225,24 @@ multiclass avx512_mask_unop_int<string IntName, string InstName> {
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}
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defm : avx512_mask_unop_int<"knot", "KNOT">;
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let Predicates = [HasDQI] in
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def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
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let Predicates = [HasAVX512] in
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def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
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let Predicates = [HasBWI] in
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def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
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let Predicates = [HasBWI] in
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def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
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// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
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let Predicates = [HasAVX512] in {
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def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
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(COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
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// With AVX-512, 8-bit mask is promoted to 16-bit mask.
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def : Pat<(not VK8:$src),
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(COPY_TO_REGCLASS
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(KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
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}
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// Mask binary operation
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// - KAND, KANDN, KOR, KXNOR, KXOR
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@ -3067,6 +3067,8 @@ static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
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inline static bool MaskRegClassContains(unsigned Reg) {
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return X86::VK8RegClass.contains(Reg) ||
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X86::VK16RegClass.contains(Reg) ||
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X86::VK32RegClass.contains(Reg) ||
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X86::VK64RegClass.contains(Reg) ||
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X86::VK1RegClass.contains(Reg);
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}
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static
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@ -5,8 +5,10 @@ define i16 @mask16(i16 %x) {
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%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <16 x i1> %m1 to i16
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ret i16 %ret
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; CHECK: mask16
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; CHECK: knotw
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; CHECK-LABEL: mask16
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; CHECK: kmovw
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw
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; CHECK: ret
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}
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@ -15,8 +17,38 @@ define i8 @mask8(i8 %x) {
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%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <8 x i1> %m1 to i8
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ret i8 %ret
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; CHECK: mask8
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; CHECK: knotw
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; CHECK-LABEL: mask8
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; CHECK: kmovw
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw
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; CHECK: ret
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}
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define void @mask16_mem(i16* %ptr) {
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%x = load i16* %ptr, align 4
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%m0 = bitcast i16 %x to <16 x i1>
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%m1 = xor <16 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <16 x i1> %m1 to i16
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store i16 %ret, i16* %ptr, align 4
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ret void
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; CHECK-LABEL: mask16_mem
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; CHECK: kmovw (%rdi), %k{{[0-7]}}
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw %k{{[0-7]}}, (%rdi)
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; CHECK: ret
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}
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define void @mask8_mem(i8* %ptr) {
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%x = load i8* %ptr, align 4
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%m0 = bitcast i8 %x to <8 x i1>
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%m1 = xor <8 x i1> %m0, <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>
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%ret = bitcast <8 x i1> %m1 to i8
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store i8 %ret, i8* %ptr, align 4
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ret void
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; CHECK-LABEL: mask8_mem
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; CHECK: kmovw (%rdi), %k{{[0-7]}}
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; CHECK-NEXT: knotw
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; CHECK-NEXT: kmovw %k{{[0-7]}}, (%rdi)
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; CHECK: ret
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}
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@ -2489,6 +2489,54 @@
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// CHECK: encoding: [0x62,0x71,0x24,0x50,0x5c,0xb2,0xfc,0xfd,0xff,0xff]
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vsubps -516(%rdx){1to16}, %zmm27, %zmm14
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// CHECK: knotw %k6, %k3
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// CHECK: encoding: [0xc5,0xf8,0x44,0xde]
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knotw %k6, %k3
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// check: kmovw %k5, %k4
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// check: encoding: [0xc5,0xf8,0x90,0xe5]
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kmovw %k5, %k4
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// check: kmovw (%rcx), %k4
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// check: encoding: [0xc5,0xf8,0x90,0x21]
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kmovw (%rcx), %k4
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// check: kmovw 291(%rax,%r14,8), %k4
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// check: encoding: [0xc4,0xa1,0x78,0x90,0xa4,0xf0,0x23,0x01,0x00,0x00]
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kmovw 291(%rax,%r14,8), %k4
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// check: kmovw %k4, (%rcx)
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// check: encoding: [0xc5,0xf8,0x91,0x21]
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kmovw %k4, (%rcx)
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// check: kmovw %k4, 291(%rax,%r14,8)
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// check: encoding: [0xc4,0xa1,0x78,0x91,0xa4,0xf0,0x23,0x01,0x00,0x00]
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kmovw %k4, 291(%rax,%r14,8)
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// check: kmovw %eax, %k3
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// check: encoding: [0xc5,0xf8,0x92,0xd8]
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kmovw %eax, %k3
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// check: kmovw %ebp, %k3
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// check: encoding: [0xc5,0xf8,0x92,0xdd]
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kmovw %ebp, %k3
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// check: kmovw %r13d, %k3
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// check: encoding: [0xc4,0xc1,0x78,0x92,0xdd]
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kmovw %r13d, %k3
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// check: kmovw %k2, %eax
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// check: encoding: [0xc5,0xf8,0x93,0xc2]
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kmovw %k2, %eax
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// check: kmovw %k2, %ebp
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||||
// check: encoding: [0xc5,0xf8,0x93,0xea]
|
||||
kmovw %k2, %ebp
|
||||
|
||||
// check: kmovw %k2, %r13d
|
||||
// check: encoding: [0xc5,0x78,0x93,0xea]
|
||||
kmovw %k2, %r13d
|
||||
|
||||
// CHECK: vpmovqb %zmm2, %xmm3
|
||||
// CHECK: encoding: [0x62,0xf2,0x7e,0x48,0x32,0xd3]
|
||||
vpmovqb %zmm2, %xmm3
|
||||
|
||||
@ -1059,6 +1059,8 @@ RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
|
||||
ENCODING("VK1", ENCODING_RM)
|
||||
ENCODING("VK8", ENCODING_RM)
|
||||
ENCODING("VK16", ENCODING_RM)
|
||||
ENCODING("VK32", ENCODING_RM)
|
||||
ENCODING("VK64", ENCODING_RM)
|
||||
errs() << "Unhandled R/M register encoding " << s << "\n";
|
||||
llvm_unreachable("Unhandled R/M register encoding");
|
||||
}
|
||||
@ -1087,6 +1089,8 @@ RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
|
||||
ENCODING("VK1", ENCODING_REG)
|
||||
ENCODING("VK8", ENCODING_REG)
|
||||
ENCODING("VK16", ENCODING_REG)
|
||||
ENCODING("VK32", ENCODING_REG)
|
||||
ENCODING("VK64", ENCODING_REG)
|
||||
ENCODING("VK1WM", ENCODING_REG)
|
||||
ENCODING("VK8WM", ENCODING_REG)
|
||||
ENCODING("VK16WM", ENCODING_REG)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user