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ARM: spot SBFX-compatbile code expressed with sign_extend_inreg

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We were assuming all SBFX-like operations would have the shl/asr form, but
often when the field being extracted is an i8 or i16, we end up with a
SIGN_EXTEND_INREG acting on a shift instead. Simple enough to check for though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213754 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-07-23 13:59:12 +00:00
parent 52aa80b068
commit afb1938c39
3 changed files with 39 additions and 2 deletions
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20
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@ -2361,6 +2361,25 @@ SDNode *ARMDAGToDAGISel::SelectV6T2BitfieldExtractOp(SDNode *N,
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
}
}
if (N->getOpcode() == ISD::SIGN_EXTEND_INREG) {
unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits();
unsigned LSB = 0;
if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRL, LSB) &&
!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SRA, LSB))
return nullptr;
if (LSB + Width > 32)
return nullptr;
SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
SDValue Ops[] = { N->getOperand(0).getOperand(0),
CurDAG->getTargetConstant(LSB, MVT::i32),
CurDAG->getTargetConstant(Width - 1, MVT::i32),
getAL(CurDAG), Reg0 };
return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops);
}
return nullptr;
}
@ -2509,6 +2528,7 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
if (SDNode *I = SelectV6T2BitfieldExtractOp(N, false))
return I;
break;
case ISD::SIGN_EXTEND_INREG:
case ISD::SRA:
if (SDNode *I = SelectV6T2BitfieldExtractOp(N, true))
return I;

18
test/CodeGen/ARM/sbfx.ll
View File

@ -45,3 +45,21 @@ entry:
%tmp2 = ashr i32 %tmp, 1
ret i32 %tmp2
}
define signext i8 @f6(i32 %a) {
; CHECK-LABEL: f6:
; CHECK: sbfx r0, r0, #23, #8
%tmp = lshr i32 %a, 23
%res = trunc i32 %tmp to i8
ret i8 %res
}
define signext i8 @f7(i32 %a) {
; CHECK-LABEL: f7:
; CHECK-NOT: sbfx
%tmp = lshr i32 %a, 25
%res = trunc i32 %tmp to i8
ret i8 %res
}

3
test/CodeGen/Thumb2/thumb2-sxt_rot.ll
View File

@ -10,8 +10,7 @@ define i32 @test0(i8 %A) {
define signext i8 @test1(i32 %A) {
; CHECK-LABEL: test1:
; CHECK: lsrs r0, r0, #8
; CHECK: sxtb r0, r0
; CHECK: sbfx r0, r0, #8, #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C