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10 bits, not 12.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-12-01 18:51:32 +00:00
parent 056745cab6
commit 3990d8f89f
3 changed files with 6 additions and 6 deletions
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4
lib/Target/ARM/ARMAsmBackend.cpp
View File

@ -64,7 +64,7 @@ protected:
// These values don't encode the low two bits since they're always zero.
// Offset by 8 just as above.
return (Value - 8) >> 2;
case ARM::fixup_arm_vfp_pcrel_12: {
case ARM::fixup_arm_vfp_pcrel_10: {
// Offset by 8 just as above.
Value = Value - 8;
bool isAdd = true;
@ -202,7 +202,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
default: llvm_unreachable("Unknown fixup kind!");
case FK_Data_4: return 4;
case ARM::fixup_arm_pcrel_12: return 3;
case ARM::fixup_arm_vfp_pcrel_12: return 3;
case ARM::fixup_arm_vfp_pcrel_10: return 3;
case ARM::fixup_arm_branch: return 3;
}
}

4
lib/Target/ARM/ARMFixupKinds.h
View File

@ -17,10 +17,10 @@ namespace ARM {
enum Fixups {
// fixup_arm_pcrel_12 - 12-bit PC relative relocation for symbol addresses
fixup_arm_pcrel_12 = FirstTargetFixupKind,
// fixup_arm_vfp_pcrel_12 - 12-bit PC relative relocation for symbol addresses
// fixup_arm_vfp_pcrel_10 - 10-bit PC relative relocation for symbol addresses
// used in VFP instructions where the lower 2 bits are not encoded (so it's
// encoded as an 8-bit immediate).
fixup_arm_vfp_pcrel_12,
fixup_arm_vfp_pcrel_10,
// fixup_arm_brnach - 24-bit PC relative relocation for direct branch
// instructions.
fixup_arm_branch,

4
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -47,7 +47,7 @@ public:
const static MCFixupKindInfo Infos[] = {
// name offset bits flags
{ "fixup_arm_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_vfp_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_vfp_pcrel_10", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_arm_movt_hi16", 0, 16, 0 },
{ "fixup_arm_movw_lo16", 0, 16, 0 },
@ -613,7 +613,7 @@ getAddrMode5OpValue(const MCInst &MI, unsigned OpIdx,
assert(MO.isExpr() && "Unexpected machine operand type!");
const MCExpr *Expr = MO.getExpr();
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_12);
MCFixupKind Kind = MCFixupKind(ARM::fixup_arm_vfp_pcrel_10);
Fixups.push_back(MCFixup::Create(0, Expr, Kind));
++MCNumCPRelocations;