mirror of
https://github.com/c64scene-ar/llvm-6502.git
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3990d8f89f
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120584 91177308-0d34-0410-b5e6-96231b3b80d8
237 lines
7.3 KiB
C++
237 lines
7.3 KiB
C++
//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmBackend.h"
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#include "ARM.h"
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#include "ARMFixupKinds.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCObjectFormat.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/Object/MachOFormat.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetRegistry.h"
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using namespace llvm;
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namespace {
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class ARMAsmBackend : public TargetAsmBackend {
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public:
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ARMAsmBackend(const Target &T) : TargetAsmBackend() {}
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bool MayNeedRelaxation(const MCInst &Inst) const;
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void RelaxInstruction(const MCInst &Inst, MCInst &Res) const;
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
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unsigned getPointerSize() const {
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return 4;
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}
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protected:
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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switch (Kind) {
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default:
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llvm_unreachable("Unknown fixup kind!");
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case FK_Data_4:
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movw_lo16:
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return Value;
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case ARM::fixup_arm_pcrel_12: {
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bool isAdd = true;
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// ARM PC-relative values are offset by 8.
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Value -= 8;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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assert ((Value < 4096) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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return Value;
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}
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case ARM::fixup_arm_branch:
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// These values don't encode the low two bits since they're always zero.
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// Offset by 8 just as above.
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return (Value - 8) >> 2;
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case ARM::fixup_arm_vfp_pcrel_10: {
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// Offset by 8 just as above.
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Value = Value - 8;
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bool isAdd = true;
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if ((int64_t)Value < 0) {
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Value = -Value;
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isAdd = false;
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}
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// These values don't encode the low two bits since they're always zero.
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Value >>= 2;
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assert ((Value < 256) && "Out of range pc-relative fixup value!");
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Value |= isAdd << 23;
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return Value;
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}
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}
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}
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};
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} // end anonymous namespace
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bool ARMAsmBackend::MayNeedRelaxation(const MCInst &Inst) const {
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// FIXME: Thumb targets, different move constant targets..
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return false;
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}
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void ARMAsmBackend::RelaxInstruction(const MCInst &Inst, MCInst &Res) const {
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assert(0 && "ARMAsmBackend::RelaxInstruction() unimplemented");
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return;
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}
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bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
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// FIXME: Zero fill for now. That's not right, but at least will get the
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// section size right.
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for (uint64_t i = 0; i != Count; ++i)
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OW->Write8(0);
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return true;
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}
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namespace {
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// FIXME: This should be in a separate file.
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// ELF is an ELF of course...
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class ELFARMAsmBackend : public ARMAsmBackend {
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MCELFObjectFormat Format;
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public:
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Triple::OSType OSType;
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ELFARMAsmBackend(const Target &T, Triple::OSType _OSType)
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: ARMAsmBackend(T), OSType(_OSType) {
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HasScatteredSymbols = true;
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}
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virtual const MCObjectFormat &getObjectFormat() const {
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return Format;
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}
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void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
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uint64_t Value) const;
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createELFObjectWriter(OS, /*Is64Bit=*/false,
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OSType, ELF::EM_ARM,
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/*IsLittleEndian=*/true,
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/*HasRelocationAddend=*/false);
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}
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};
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// Fixme: can we raise this to share code between Darwin and ELF?
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void ELFARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
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uint64_t Value) const {
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uint32_t Mask = 0;
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// Fixme: 2 for Thumb
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unsigned NumBytes = 4;
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Value = adjustFixupValue(Fixup.getKind(), Value);
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switch (Fixup.getKind()) {
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default: assert(0 && "Unsupported Fixup kind"); break;
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case ARM::fixup_arm_branch: {
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unsigned Lo24 = Value & 0xFFFFFF;
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Mask = ~(0xFFFFFF);
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Value = Lo24;
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}; break;
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case ARM::fixup_arm_movt_hi16:
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case ARM::fixup_arm_movw_lo16: {
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unsigned Hi4 = (Value & 0xF000) >> 12;
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unsigned Lo12 = Value & 0x0FFF;
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// inst{19-16} = Hi4;
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// inst{11-0} = Lo12;
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Value = (Hi4 << 16) | (Lo12);
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Mask = ~(0xF0FFF);
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}; break;
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}
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assert((Fixup.getOffset() % NumBytes == 0)
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&& "Offset mod NumBytes is nonzero!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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// The Value has been "split up" into the appropriate bitfields above.
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// Fixme: how to share code with the .td generated code?
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for (unsigned i = 0; i != NumBytes; ++i) {
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DF.getContents()[Fixup.getOffset() + i] &= uint8_t(Mask >> (i * 8));
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DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
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}
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}
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namespace {
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// FIXME: This should be in a separate file.
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class DarwinARMAsmBackend : public ARMAsmBackend {
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MCMachOObjectFormat Format;
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public:
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DarwinARMAsmBackend(const Target &T) : ARMAsmBackend(T) {
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HasScatteredSymbols = true;
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}
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virtual const MCObjectFormat &getObjectFormat() const {
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return Format;
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}
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void ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
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uint64_t Value) const;
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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// FIXME: Subtarget info should be derived. Force v7 for now.
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return createMachObjectWriter(OS, /*Is64Bit=*/false,
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object::mach::CTM_ARM,
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object::mach::CSARM_V7,
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/*IsLittleEndian=*/true);
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}
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virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
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return false;
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}
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};
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} // end anonymous namespace
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static unsigned getFixupKindNumBytes(unsigned Kind) {
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switch (Kind) {
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default: llvm_unreachable("Unknown fixup kind!");
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case FK_Data_4: return 4;
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case ARM::fixup_arm_pcrel_12: return 3;
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case ARM::fixup_arm_vfp_pcrel_10: return 3;
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case ARM::fixup_arm_branch: return 3;
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}
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}
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void DarwinARMAsmBackend::ApplyFixup(const MCFixup &Fixup, MCDataFragment &DF,
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uint64_t Value) const {
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unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
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Value = adjustFixupValue(Fixup.getKind(), Value);
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assert(Fixup.getOffset() + NumBytes <= DF.getContents().size() &&
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"Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned i = 0; i != NumBytes; ++i)
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DF.getContents()[Fixup.getOffset() + i] |= uint8_t(Value >> (i * 8));
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}
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} // end anonymous namespace
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TargetAsmBackend *llvm::createARMAsmBackend(const Target &T,
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const std::string &TT) {
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switch (Triple(TT).getOS()) {
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case Triple::Darwin:
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return new DarwinARMAsmBackend(T);
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case Triple::MinGW32:
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case Triple::Cygwin:
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case Triple::Win32:
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assert(0 && "Windows not supported on ARM");
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default:
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return new ELFARMAsmBackend(T, Triple(TT).getOS());
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}
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}
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