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Modify the ISD::ADD opcode case to use new immediate constant predicates.

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Includes support for 32-bit constants using addi/addis.

Patch by Jim Laskey.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-08 21:21:03 +00:00
parent 8fd1980ce6
commit 39c6896d22
1 changed files with 15 additions and 11 deletions
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26
lib/Target/PowerPC/PPCISelPattern.cpp
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@ -1689,19 +1689,23 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
return Result;
}
Tmp1 = SelectExpr(N.getOperand(0));
switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
default: assert(0 && "unhandled result code");
case 0: // No immediate
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
break;
case 1: // Low immediate
if (isImmediate(N.getOperand(1), Tmp2)) {
Tmp3 = HA16(Tmp2);
Tmp2 = Lo16(Tmp2);
if (Tmp2 && Tmp3) {
unsigned Reg = MakeReg(MVT::i32);
BuildMI(BB, PPC::ADDI, 2, Reg).addReg(Tmp1).addSImm(Tmp2);
BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Reg).addSImm(Tmp3);
} else if (Tmp2) {
BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
break;
case 2: // Shifted immediate
BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
break;
} else {
BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp3);
}
return Result;
}
Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
return Result;
case ISD::AND: