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[AArch64] Fix bad register class constraint in fast-isel for TST instruction.

Browse Source 
rdar://problem/20748715


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236273 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet 2015-04-30 22:27:20 +00:00
parent d47066e86b
commit 3a0fccf6a0
2 changed files with 14 additions and 1 deletions
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5
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -2679,8 +2679,11 @@ bool AArch64FastISel::selectSelect(const Instruction *I) {
return false;
bool CondIsKill = hasTrivialKill(Cond);
const MCInstrDesc &II = TII.get(AArch64::ANDSWri);
CondReg = constrainOperandRegClass(II, CondReg, 1);
// Emit a TST instruction (ANDS wzr, reg, #imm).
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ANDSWri),
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
AArch64::WZR)
.addReg(CondReg, getKillRegState(CondIsKill))
.addImm(AArch64_AM::encodeLogicalImmediate(1, 32));

10
test/CodeGen/AArch64/arm64-fast-isel.ll
View File

@ -91,3 +91,13 @@ define void @t6() nounwind {
}
declare void @llvm.trap() nounwind
define void @ands(i32* %addr) {
; CHECK-LABEL: ands:
; CHECK: tst [[COND:w[0-9]+]], #0x1
; CHECK-NEXT: csel [[COND]],
entry:
%cond91 = select i1 undef, i32 1, i32 2
store i32 %cond91, i32* %addr, align 4
ret void
}