mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-21 18:29:45 +00:00
Remove fadd(fmul) patterns for FMA3. This needs to be implemented by paying attention to FP_CONTRACT and matching @llvm.fma which is not available yet. This will allow us to enablle intrinsic use at least though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157804 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
78fc72d0f1
commit
3a8172ad8d
@ -113,162 +113,6 @@ let ExeDomain = SSEPackedDouble in {
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memopv4f64, int_x86_fma4_vfnmsub_pd, int_x86_fma4_vfnmsub_pd_256>, VEX_W;
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}
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let Predicates = [HasFMA3], AddedComplexity = 20 in {
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//------------
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// FP double precision ADD - 256
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//------------
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// FMA231: src1 = src2*src3 + src1
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def : Pat<(v4f64 (fadd (fmul VR256:$src2, (memopv4f64 addr:$src3)), VR256:$src1)),
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(VFMADDPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA231: src1 = src2*src3 + src1
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def : Pat<(v4f64 (fadd (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
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(VFMADDPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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//------------
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// FP double precision ADD - 128
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//------------
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// FMA231: src1 = src2*src3 + src1
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def : Pat<(v2f64 (fadd (fmul VR128:$src2, (memopv2f64 addr:$src3)), VR128:$src1)),
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(VFMADDPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;
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// FMA231: src1 = src2*src3 + src1
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def : Pat<(v2f64 (fadd (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
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(VFMADDPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
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//------------
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// FP double precision SUB - 256
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//------------
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// FMA231: src1 = src2*src3 - src1
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def : Pat<(v4f64 (fsub (fmul VR256:$src2, (memopv4f64 addr:$src3)), VR256:$src1)),
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(VFMSUBPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA231: src1 = src2*src3 - src1
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def : Pat<(v4f64 (fsub (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
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(VFMSUBPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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//------------
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// FP double precision SUB - 128
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//------------
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// FMA231: src1 = src2*src3 - src1
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def : Pat<(v2f64 (fsub (fmul VR128:$src2, (memopv2f64 addr:$src3)), VR128:$src1)),
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(VFMSUBPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;
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// FMA231: src1 = src2*src3 - src1
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def : Pat<(v2f64 (fsub (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
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(VFMSUBPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
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//------------
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// FP double precision FNMADD - 256
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//------------
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// FMA231: src1 = - src2*src3 + src1
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def : Pat<(v4f64 (fsub VR256:$src1, (fmul VR256:$src2, (memopv4f64 addr:$src3)))),
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(VFNMADDPDr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA231: src1 = - src2*src3 + src1
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def : Pat<(v4f64 (fsub VR256:$src1, (fmul VR256:$src2, VR256:$src3))),
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(VFNMADDPDr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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//------------
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// FP double precision FNMADD - 128
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//------------
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// FMA231: src1 = - src2*src3 + src1
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def : Pat<(v2f64 (fsub VR128:$src1, (fmul VR128:$src2, (memopv2f64 addr:$src3)))),
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(VFNMADDPDr231m VR128:$src1, VR128:$src2, addr:$src3)>;
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// FMA231: src1 = - src2*src3 + src1
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def : Pat<(v2f64 (fsub VR128:$src1, (fmul VR128:$src2, VR128:$src3))),
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(VFNMADDPDr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
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//------------
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// FP single precision ADD - 256
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//------------
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// FMA231: src1 = src2*src3 + src1
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def : Pat<(v8f32 (fadd (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
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(VFMADDPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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// FMA213 : src1 = src2*src1 + src3
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def : Pat<(v8f32 (fadd (fmul VR256:$src1, VR256:$src2), (memopv8f32 addr:$src3))),
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(VFMADDPSr213mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA231: src1 = src2*src3 + src1
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def : Pat<(v8f32 (fadd (fmul (memopv8f32 addr:$src3), VR256:$src2), VR256:$src1)),
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(VFMADDPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA213: src1 = src2*src1 + src3
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def : Pat<(v8f32 (fadd (fmul VR256:$src2, VR256:$src1), VR256:$src3)),
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(VFMADDPSr213rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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//------------
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// FP single precision ADD - 128
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//------------
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// FMA231 : src1 = src2*src3 + src1
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def : Pat<(v4f32 (fadd (fmul VR128:$src2, (memopv4f32 addr:$src3)), VR128:$src1)),
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(VFMADDPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;
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// FMA231 : src1 = src2*src3 + src1
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def : Pat<(v4f32 (fadd (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
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(VFMADDPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
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//------------
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// FP single precision SUB - 256
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//------------
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// FMA231: src1 = src2*src3 - src1
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def : Pat<(v8f32 (fsub (fmul VR256:$src2, (memopv8f32 addr:$src3)), VR256:$src1)),
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(VFMSUBPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA231: src1 = src2*src3 - src1
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def : Pat<(v8f32 (fsub (fmul VR256:$src2, VR256:$src3), VR256:$src1)),
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(VFMSUBPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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//------------
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// FP single precision SUB - 128
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//------------
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// FMA231 : src1 = src2*src3 - src1
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def : Pat<(v4f32 (fsub (fmul VR128:$src2, (memopv4f32 addr:$src3)), VR128:$src1)),
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(VFMSUBPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;
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// FMA231 : src1 = src2*src3 - src1
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def : Pat<(v4f32 (fsub (fmul VR128:$src2, VR128:$src3), VR128:$src1)),
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(VFMSUBPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
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//------------
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// FP single precision FNMADD - 256
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//------------
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// FMA231: src1 = - src2*src3 + src1
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def : Pat<(v8f32 (fsub VR256:$src1, (fmul VR256:$src2, (memopv8f32 addr:$src3)))),
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(VFNMADDPSr231mY VR256:$src1, VR256:$src2, addr:$src3)>;
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// FMA231: src1 = - src2*src3 + src1
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def : Pat<(v8f32 (fsub VR256:$src1, (fmul VR256:$src2, VR256:$src3))),
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(VFNMADDPSr231rY VR256:$src1, VR256:$src2, VR256:$src3)>;
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//------------
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// FP single precision FNMADD - 128
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//------------
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// FMA231 : src1 = src2*src3 - src1
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def : Pat<(v4f32 (fsub VR128:$src1, (fmul VR128:$src2, (memopv4f32 addr:$src3)))),
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(VFNMADDPSr231m VR128:$src1, VR128:$src2, addr:$src3)>;
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// FMA231 : src1 = src2*src3 - src1
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def : Pat<(v4f32 (fsub VR128:$src1, (fmul VR128:$src2, VR128:$src3))),
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(VFNMADDPSr231r VR128:$src1, VR128:$src2, VR128:$src3)>;
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} // HasFMA3
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//------------------------------
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// SCALAR
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//------------------------------
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let Constraints = "$src1 = $dst" in {
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multiclass fma3s_rm<bits<8> opc, string OpcodeStr, X86MemOperand x86memop,
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@ -328,62 +172,6 @@ defm VFNMSUBSD : fma3s_forms<0x9F, 0xAF, 0xBF, "vfnmsub", "sd", f64mem, FR64,
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int_x86_fma4_vfnmsub_sd>, VEX_W, VEX_LIG;
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let Predicates = [HasFMA3], AddedComplexity = 20 in {
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//------------
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// FP scalar ADD
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//------------
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// FMADD231 : src1 = src2*src3 + src1
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def : Pat<(f32 (fadd (fmul FR32:$src2, FR32:$src3), FR32:$src1)),
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(VFMADDSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;
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def : Pat<(f32 (fadd (fmul FR32:$src2, (loadf32 addr:$src3)), FR32:$src1)),
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(VFMADDSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;
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def : Pat<(f64 (fadd (fmul FR64:$src2, FR64:$src3), FR64:$src1)),
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(VFMADDSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;
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def : Pat<(f64 (fadd (fmul FR64:$src2, (loadf64 addr:$src3)), FR64:$src1)),
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(VFMADDSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;
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//------------
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// FP scalar SUB src2*src3 - src1
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//------------
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def : Pat<(f32 (fsub (fmul FR32:$src2, FR32:$src3), FR32:$src1)),
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(VFMSUBSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;
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def : Pat<(f32 (fsub (fmul FR32:$src2, (loadf32 addr:$src3)), FR32:$src1)),
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(VFMSUBSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;
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def : Pat<(f64 (fsub (fmul FR64:$src2, FR64:$src3), FR64:$src1)),
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(VFMSUBSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;
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def : Pat<(f64 (fsub (fmul FR64:$src2, (loadf64 addr:$src3)), FR64:$src1)),
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(VFMSUBSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;
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//------------
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// FP scalar NADD src1 - src2*src3
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//------------
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def : Pat<(f32 (fsub FR32:$src1, (fmul FR32:$src2, FR32:$src3))),
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(VFNMADDSSr231r FR32:$src1, FR32:$src2, FR32:$src3)>;
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def : Pat<(f32 (fsub FR32:$src1, (fmul FR32:$src2, (loadf32 addr:$src3)))),
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(VFNMADDSSr231m FR32:$src1, FR32:$src2, addr:$src3)>;
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def : Pat<(f64 (fsub FR64:$src1, (fmul FR64:$src2, FR64:$src3))),
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(VFNMADDSDr231r FR64:$src1, FR64:$src2, FR64:$src3)>;
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def : Pat<(f64 (fsub FR64:$src1, (fmul FR64:$src2, (loadf64 addr:$src3)))),
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(VFNMADDSDr231m FR64:$src1, FR64:$src2, addr:$src3)>;
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} // HasFMA3
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//===----------------------------------------------------------------------===//
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// FMA4 - AMD 4 operand Fused Multiply-Add instructions
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//===----------------------------------------------------------------------===//
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@ -1,66 +0,0 @@
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; RUN: llc < %s -mtriple=x86_64-pc-win32 -mcpu=core-avx2 -mattr=avx2,+fma3 | FileCheck %s
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define <4 x float> @test_x86_fmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
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; CHECK: fmadd231ps {{.*\(%r.*}}, %xmm
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%x = fmul <4 x float> %a0, %a1
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%res = fadd <4 x float> %x, %a2
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ret <4 x float> %res
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}
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define <4 x float> @test_x86_fmsub_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
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; CHECK: fmsub231ps {{.*\(%r.*}}, %xmm
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%x = fmul <4 x float> %a0, %a1
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%res = fsub <4 x float> %x, %a2
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ret <4 x float> %res
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}
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define <4 x float> @test_x86_fnmadd_ps(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2) {
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; CHECK: fnmadd231ps {{.*\(%r.*}}, %xmm
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%x = fmul <4 x float> %a0, %a1
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%res = fsub <4 x float> %a2, %x
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ret <4 x float> %res
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}
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define <8 x float> @test_x86_fmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
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; CHECK: vfmadd213ps {{.*\(%r.*}}, %ymm
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%x = fmul <8 x float> %a0, %a1
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%res = fadd <8 x float> %x, %a2
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ret <8 x float> %res
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}
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define <4 x double> @test_x86_fmadd_pd_y(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
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; CHECK: vfmadd231pd {{.*\(%r.*}}, %ymm
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%x = fmul <4 x double> %a0, %a1
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%res = fadd <4 x double> %x, %a2
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ret <4 x double> %res
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}
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define <8 x float> @test_x86_fmsub_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
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; CHECK: fmsub231ps {{.*\(%r.*}}, %ymm
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%x = fmul <8 x float> %a0, %a1
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%res = fsub <8 x float> %x, %a2
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ret <8 x float> %res
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}
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define <8 x float> @test_x86_fnmadd_ps_y(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
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; CHECK: fnmadd231ps {{.*\(%r.*}}, %ymm
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%x = fmul <8 x float> %a0, %a1
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%res = fsub <8 x float> %a2, %x
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ret <8 x float> %res
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}
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define float @test_x86_fnmadd_ss(float %a0, float %a1, float %a2) {
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; CHECK: vfnmadd231ss %xmm1, %xmm0, %xmm2
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%x = fmul float %a0, %a1
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%res = fsub float %a2, %x
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ret float %res
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}
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define double @test_x86_fnmadd_sd(double %a0, double %a1, double %a2) {
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; CHECK: vfnmadd231sd %xmm1, %xmm0, %xmm2
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%x = fmul double %a0, %a1
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%res = fsub double %a2, %x
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ret double %res
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}
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