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Implement brind operator for mips16.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166903 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Reed Kotler 2012-10-28 23:08:07 +00:00
parent 0d91c0b519
commit 3a9f4568fb
2 changed files with 59 additions and 0 deletions
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19
lib/Target/Mips/Mips16InstrInfo.td
View File

@ -250,6 +250,12 @@ class FRR16_JALRC_RA_only_ins<bits<1> nd_, bits<1> l_,
FRR16_JALRC<nd_, l_, 1, (outs), (ins), !strconcat(asmstr, "\t $$ra"),
[], itin> ;
class FRR16_JALRC_ins<bits<1> nd, bits<1> l, bits<1> ra,
string asmstr, InstrItinClass itin>:
FRR16_JALRC<nd, l, ra, (outs), (ins CPU16Regs:$rx),
!strconcat(asmstr, "\t $rx"), [], itin> ;
//
// RRR-type instruction format
//
@ -508,6 +514,13 @@ def JrRa16: FRR16_JALRC_RA_only_ins<0, 0, "jr", IIAlu> {
let isTerminator=1;
let isBarrier=1;
}
def JrcRx16: FRR16_JALRC_ins<1, 1, 0, "jrc", IIAlu> {
let isBranch = 1;
let isIndirectBranch = 1;
let isTerminator=1;
let isBarrier=1;
}
//
// Format: LB ry, offset(rx) MIPS16e
// Purpose: Load Byte (Extended)
@ -991,6 +1004,12 @@ class UncondBranch16_pat<SDNode OpNode, Instruction I>:
let Predicates = [RelocPIC, InMips16Mode];
}
// Indirect branch
def: Mips16Pat<
(brind CPU16Regs:$rs),
(JrcRx16 CPU16Regs:$rs)>;
// Jump and Link (Call)
let isCall=1, hasDelaySlot=1 in
def JumpLinkReg16:

40
test/CodeGen/Mips/brind.ll Normal file
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@ -0,0 +1,40 @@
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
@main.L = internal unnamed_addr constant [5 x i8*] [i8* blockaddress(@main, %L1), i8* blockaddress(@main, %L2), i8* blockaddress(@main, %L3), i8* blockaddress(@main, %L4), i8* null], align 4
@str = private unnamed_addr constant [2 x i8] c"A\00"
@str5 = private unnamed_addr constant [2 x i8] c"B\00"
@str6 = private unnamed_addr constant [2 x i8] c"C\00"
@str7 = private unnamed_addr constant [2 x i8] c"D\00"
@str8 = private unnamed_addr constant [2 x i8] c"E\00"
define i32 @main() nounwind {
entry:
%puts = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str, i32 0, i32 0))
br label %L1
L1: ; preds = %entry, %L3
%i.0 = phi i32 [ 0, %entry ], [ %inc, %L3 ]
%puts5 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str5, i32 0, i32 0))
br label %L2
L2: ; preds = %L1, %L3
%i.1 = phi i32 [ %i.0, %L1 ], [ %inc, %L3 ]
%puts6 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str6, i32 0, i32 0))
br label %L3
L3: ; preds = %L2, %L3
%i.2 = phi i32 [ %i.1, %L2 ], [ %inc, %L3 ]
%puts7 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str7, i32 0, i32 0))
%inc = add i32 %i.2, 1
%arrayidx = getelementptr inbounds [5 x i8*]* @main.L, i32 0, i32 %i.2
%0 = load i8** %arrayidx, align 4
indirectbr i8* %0, [label %L1, label %L2, label %L3, label %L4]
; 16: jrc ${{[0-9]+}}
L4: ; preds = %L3
%puts8 = tail call i32 @puts(i8* getelementptr inbounds ([2 x i8]* @str8, i32 0, i32 0))
ret i32 0
}
declare i32 @puts(i8* nocapture) nounwind