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https://github.com/c64scene-ar/llvm-6502.git
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add shifts to addressing mode 1
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30291 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -41,6 +41,16 @@ namespace llvm {
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};
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}
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namespace ARMShift {
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enum ShiftTypes {
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LSL,
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LSR,
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ASR,
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ROR,
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RRX
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};
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}
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static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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@ -158,13 +158,38 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
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}
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void ARMAsmPrinter::printAddrMode1(const MachineInstr *MI, int opNum) {
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const MachineOperand &MO1 = MI->getOperand(opNum);
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const MachineOperand &Arg = MI->getOperand(opNum);
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const MachineOperand &Shift = MI->getOperand(opNum + 1);
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const MachineOperand &ShiftType = MI->getOperand(opNum + 2);
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if(MO1.isImmediate()) {
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if(Arg.isImmediate()) {
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assert(Shift.getImmedValue() == 0);
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printOperand(MI, opNum);
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} else {
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assert(MO1.isRegister());
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assert(Arg.isRegister());
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printOperand(MI, opNum);
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if(Shift.isRegister() || Shift.getImmedValue() != 0) {
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const char *s = NULL;
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switch(ShiftType.getImmedValue()) {
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case ARMShift::LSL:
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s = ", lsl ";
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break;
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case ARMShift::LSR:
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s = ", lsr ";
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break;
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case ARMShift::ASR:
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s = ", asr ";
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break;
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case ARMShift::ROR:
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s = ", ror ";
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break;
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case ARMShift::RRX:
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s = ", rrx ";
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break;
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}
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O << s;
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printOperand(MI, opNum + 1);
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}
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}
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}
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@ -445,7 +445,8 @@ public:
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SDNode *Select(SDOperand Op);
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
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bool SelectAddrMode1(SDOperand N, SDOperand &Arg);
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bool SelectAddrMode1(SDOperand N, SDOperand &Arg, SDOperand &Shift,
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SDOperand &ShiftType);
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// Include the pieces autogenerated from the target description.
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#include "ARMGenDAGISel.inc"
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@ -480,17 +481,38 @@ static bool isInt12Immediate(SDOperand Op, short &Imm) {
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}
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bool ARMDAGToDAGISel::SelectAddrMode1(SDOperand N,
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SDOperand &Arg) {
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SDOperand &Arg,
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SDOperand &Shift,
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SDOperand &ShiftType) {
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switch(N.getOpcode()) {
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case ISD::Constant: {
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//TODO:check that we have a valid constant
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int32_t t = cast<ConstantSDNode>(N)->getValue();
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Arg = CurDAG->getTargetConstant(t, MVT::i32);
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Arg = CurDAG->getTargetConstant(t, MVT::i32);
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Shift = CurDAG->getTargetConstant(0, MVT::i32);
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ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
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return true;
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}
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case ISD::SRA:
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Arg = N.getOperand(0);
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Shift = N.getOperand(1);
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ShiftType = CurDAG->getTargetConstant(ARMShift::ASR, MVT::i32);
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return true;
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case ISD::SRL:
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Arg = N.getOperand(0);
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Shift = N.getOperand(1);
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ShiftType = CurDAG->getTargetConstant(ARMShift::LSR, MVT::i32);
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return true;
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case ISD::SHL:
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Arg = N.getOperand(0);
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Shift = N.getOperand(1);
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ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
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return true;
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}
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Arg = N;
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Arg = N;
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Shift = CurDAG->getTargetConstant(0, MVT::i32);
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ShiftType = CurDAG->getTargetConstant(ARMShift::LSL, MVT::i32);
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return true;
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}
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@ -33,15 +33,18 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg) const {
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MachineOpCode oc = MI.getOpcode();
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switch (oc) {
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case ARM::MOV:
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assert(MI.getNumOperands() == 2 &&
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case ARM::MOV: {
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assert(MI.getNumOperands() == 4 &&
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MI.getOperand(0).isRegister() &&
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"Invalid ARM MOV instruction");
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if (MI.getOperand(1).isRegister()) {
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const MachineOperand &Arg = MI.getOperand(1);
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const MachineOperand &Shift = MI.getOperand(2);
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if (Arg.isRegister() && Shift.isImmediate() && Shift.getImmedValue() == 0) {
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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return true;
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}
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}
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}
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return false;
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}
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@ -15,8 +15,8 @@
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// Address operands
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def op_addr_mode1 : Operand<iPTR> {
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let PrintMethod = "printAddrMode1";
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let NumMIOperands = 1;
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let MIOperandInfo = (ops ptr_rc);
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let NumMIOperands = 3;
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let MIOperandInfo = (ops ptr_rc, ptr_rc, i32imm);
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}
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def memri : Operand<iPTR> {
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@ -27,7 +27,7 @@ def memri : Operand<iPTR> {
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// Define ARM specific addressing mode.
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//Addressing Mode 1: data processing operands
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def addr_mode1 : ComplexPattern<iPTR, 1, "SelectAddrMode1", [imm]>;
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def addr_mode1 : ComplexPattern<iPTR, 3, "SelectAddrMode1", [imm, sra, shl, srl]>;
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//register plus/minus 12 bit offset
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def iaddr : ComplexPattern<iPTR, 2, "SelectAddrRegImm", [frameindex]>;
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@ -119,21 +119,6 @@ def AND : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"and $dst, $a, $b",
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[(set IntRegs:$dst, (and IntRegs:$a, addr_mode1:$b))]>;
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// All arm data processing instructions have a shift. Maybe we don't have
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// to implement this
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def SHL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"mov $dst, $a, lsl $b",
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[(set IntRegs:$dst, (shl IntRegs:$a, IntRegs:$b))]>;
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def SRA : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"mov $dst, $a, asr $b",
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[(set IntRegs:$dst, (sra IntRegs:$a, IntRegs:$b))]>;
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def SRL : InstARM<(ops IntRegs:$dst, IntRegs:$a, IntRegs:$b),
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"mov $dst, $a, lsr $b",
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[(set IntRegs:$dst, (srl IntRegs:$a, IntRegs:$b))]>;
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def EOR : InstARM<(ops IntRegs:$dst, IntRegs:$a, op_addr_mode1:$b),
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"eor $dst, $a, $b",
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[(set IntRegs:$dst, (xor IntRegs:$a, addr_mode1:$b))]>;
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@ -48,7 +48,8 @@ void ARMRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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assert (RC == ARM::IntRegsRegisterClass);
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BuildMI(MBB, I, ARM::MOV, 1, DestReg).addReg(SrcReg);
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BuildMI(MBB, I, ARM::MOV, 3, DestReg).addReg(SrcReg).addImm(0)
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.addImm(ARMShift::LSL);
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}
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MachineInstr *ARMRegisterInfo::foldMemoryOperand(MachineInstr* MI,
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@ -114,7 +115,8 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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// Insert a set of r12 with the full address
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// r12 = r13 + offset
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MachineBasicBlock *MBB2 = MI.getParent();
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BuildMI(*MBB2, II, ARM::ADD, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
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BuildMI(*MBB2, II, ARM::ADD, 4, ARM::R12).addReg(ARM::R13).addImm(Offset)
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.addImm(0).addImm(ARMShift::LSL);
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// Replace the FrameIndex with r12
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MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12, false);
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@ -140,7 +142,8 @@ void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MFI->setStackSize(NumBytes);
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//sub sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::SUB, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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BuildMI(MBB, MBBI, ARM::SUB, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
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.addImm(0).addImm(ARMShift::LSL);
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}
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void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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@ -153,7 +156,8 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
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int NumBytes = (int) MFI->getStackSize();
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//add sp, sp, #NumBytes
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BuildMI(MBB, MBBI, ARM::ADD, 2, ARM::R13).addReg(ARM::R13).addImm(NumBytes);
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BuildMI(MBB, MBBI, ARM::ADD, 4, ARM::R13).addReg(ARM::R13).addImm(NumBytes)
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.addImm(0).addImm(ARMShift::LSL);
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}
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unsigned ARMRegisterInfo::getRARegister() const {
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