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Fix XCoreTargetLowering::isLegalAddressingMode to handle non simple VTs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2009-07-15 15:46:56 +00:00
parent f301c2299c
commit 3af282f16a
2 changed files with 17 additions and 24 deletions
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34
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -874,44 +874,30 @@ static inline bool isImmUs4(int64_t val)
bool
XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const {
MVT VT = getValueType(Ty, true);
// Get expected value type after legalization
switch (VT.getSimpleVT()) {
// Legal load / stores
case MVT::i8:
case MVT::i16:
case MVT::i32:
break;
// Expand i1 -> i8
case MVT::i1:
VT = MVT::i8;
break;
// Everything else is lowered to words
default:
VT = MVT::i32;
break;
}
const TargetData *TD = TM.getTargetData();
unsigned Size = TD->getTypeAllocSize(Ty);
if (AM.BaseGV) {
return VT == MVT::i32 && !AM.HasBaseReg && AM.Scale == 0 &&
return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
AM.BaseOffs%4 == 0;
}
switch (VT.getSimpleVT()) {
default:
return false;
case MVT::i8:
switch (Size) {
case 1:
// reg + imm
if (AM.Scale == 0) {
return isImmUs(AM.BaseOffs);
}
// reg + reg
return AM.Scale == 1 && AM.BaseOffs == 0;
case MVT::i16:
case 2:
case 3:
// reg + imm
if (AM.Scale == 0) {
return isImmUs2(AM.BaseOffs);
}
// reg + reg<<1
return AM.Scale == 2 && AM.BaseOffs == 0;
case MVT::i32:
default:
// reg + imm
if (AM.Scale == 0) {
return isImmUs4(AM.BaseOffs);

7
test/CodeGen/XCore/2009-07-15-store192.ll Normal file
View File

@ -0,0 +1,7 @@
; RUN: llvm-as < %s | llc -march=xcore > %t1.s
define void @store32(i8* %p) nounwind {
entry:
%0 = bitcast i8* %p to i192*
store i192 0, i192* %0, align 4
ret void
}