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[AArch64] Add support for NEON scalar three register different instruction
class. The instruction class includes the signed saturating doubling multiply-add long, signed saturating doubling multiply-subtract long, and the signed saturating doubling multiply long instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192908 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -204,4 +204,13 @@ def int_aarch64_neon_vabs :
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// Scalar Negate Value
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def int_aarch64_neon_vneg :
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Intrinsic<[llvm_v1i64_ty], [llvm_v1i64_ty], [IntrNoMem]>;
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// Signed Saturating Doubling Multiply-Add Long
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def int_aarch64_neon_vqdmlal : Neon_2Arg_Long_Intrinsic;
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// Signed Saturating Doubling Multiply-Subtract Long
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def int_aarch64_neon_vqdmlsl : Neon_2Arg_Long_Intrinsic;
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// Signed Saturating Doubling Multiply Long
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def int_aarch64_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
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}
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@ -1212,5 +1212,23 @@ class NeonI_LdStMult<bit q, bit l, bits<4> opcode, bits<2> size,
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// Inherit Rt in 4-0
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}
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// Format AdvSIMD 3 scalar registers with different type
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class NeonI_Scalar3Diff<bit u, bits<2> size, bits<4> opcode,
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dag outs, dag ins, string asmstr,
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list<dag> patterns, InstrItinClass itin>
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: A64InstRdnm<outs, ins, asmstr, patterns, itin> {
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let Inst{31-30} = 0b01;
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let Inst{29} = u;
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let Inst{28-24} = 0b11110;
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let Inst{23-22} = size;
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let Inst{21} = 0b1;
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// Inherit Rm in 20-16
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let Inst{15-12} = opcode;
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let Inst{11-10} = 0b00;
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// Inherit Rn in 9-5
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// Inherit Rd in 4-0
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}
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}
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@ -3231,6 +3231,30 @@ multiclass Neon_Scalar3Same_SD_size_patterns<SDPatternOperator opnode,
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(INSTD FPR64:$Rn, FPR64:$Rm)>;
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}
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// Scalar Three Different
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multiclass NeonI_Scalar3Diff_HS_size<bit u, bits<4> opcode, string asmop> {
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def shh : NeonI_Scalar3Diff<u, 0b01, opcode,
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(outs FPR32:$Rd), (ins FPR16:$Rn, FPR16:$Rm),
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!strconcat(asmop, " $Rd, $Rn, $Rm"),
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[],
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NoItinerary>;
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def dss : NeonI_Scalar3Diff<u, 0b10, opcode,
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(outs FPR64:$Rd), (ins FPR32:$Rn, FPR32:$Rm),
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!strconcat(asmop, " $Rd, $Rn, $Rm"),
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[],
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NoItinerary>;
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}
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multiclass Neon_Scalar3Diff_HS_size_patterns<SDPatternOperator opnode,
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Instruction INSTH,
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Instruction INSTS> {
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def : Pat<(v1i32 (opnode (v1i16 FPR16:$Rn), (v1i16 FPR16:$Rm))),
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(INSTH FPR16:$Rn, FPR16:$Rm)>;
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def : Pat<(v1i64 (opnode (v1i32 FPR32:$Rn), (v1i32 FPR32:$Rm))),
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(INSTS FPR32:$Rn, FPR32:$Rm)>;
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}
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// Scalar Two Registers Miscellaneous
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multiclass NeonI_Scalar2SameMisc_SD_size<bit u, bit size_high, bits<5> opcode,
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@ -3498,6 +3522,21 @@ defm : Neon_Scalar3Same_BHSD_size_patterns<int_aarch64_neon_vqrshlu, UQRSHLbbb,
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshifts, SQRSHLddd>;
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defm : Neon_Scalar3Same_D_size_patterns<int_arm_neon_vqrshiftu, UQRSHLddd>;
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// Signed Saturating Doubling Multiply-Add Long
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defm SQDMLAL : NeonI_Scalar3Diff_HS_size<0b0, 0b1001, "sqdmlal">;
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defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmlal,
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SQDMLALshh, SQDMLALdss>;
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// Signed Saturating Doubling Multiply-Subtract Long
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defm SQDMLSL : NeonI_Scalar3Diff_HS_size<0b0, 0b1011, "sqdmlsl">;
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defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmlsl,
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SQDMLSLshh, SQDMLSLdss>;
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// Signed Saturating Doubling Multiply Long
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defm SQDMULL : NeonI_Scalar3Diff_HS_size<0b0, 0b1101, "sqdmull">;
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defm : Neon_Scalar3Diff_HS_size_patterns<int_aarch64_neon_vqdmull,
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SQDMULLshh, SQDMULLdss>;
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// Scalar Signed Integer Convert To Floating-point
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defm SCVTF : NeonI_Scalar2SameMisc_SD_size<0b0, 0b0, 0b11101, "scvtf">;
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defm : Neon_Scalar2SameMisc_cvt_SD_size_patterns<int_aarch64_neon_vcvtf32_s32,
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@ -68,3 +68,78 @@ define double @test_vmulxd_f64(double %a, double %b) {
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declare <1 x float> @llvm.aarch64.neon.vmulx.v1f32(<1 x float>, <1 x float>)
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declare <1 x double> @llvm.aarch64.neon.vmulx.v1f64(<1 x double>, <1 x double>)
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define i32 @test_vqdmlalh_s16(i16 %a, i16 %b) {
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; CHECK: test_vqdmlalh_s16
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; CHECK: sqdmlal {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vqdmlal.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqdmlal1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vqdmlal2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16> %vqdmlal.i, <1 x i16> %vqdmlal1.i)
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%0 = extractelement <1 x i32> %vqdmlal2.i, i32 0
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ret i32 %0
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}
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define i64 @test_vqdmlals_s32(i32 %a, i32 %b) {
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; CHECK: test_vqdmlals_s32
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; CHECK: sqdmlal {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vqdmlal.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vqdmlal1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vqdmlal2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32> %vqdmlal.i, <1 x i32> %vqdmlal1.i)
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%0 = extractelement <1 x i64> %vqdmlal2.i, i32 0
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ret i64 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vqdmlal.v1i32(<1 x i16>, <1 x i16>)
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declare <1 x i64> @llvm.aarch64.neon.vqdmlal.v1i64(<1 x i32>, <1 x i32>)
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define i32 @test_vqdmlslh_s16(i16 %a, i16 %b) {
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; CHECK: test_vqdmlslh_s16
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; CHECK: sqdmlsl {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vqdmlsl.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqdmlsl1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vqdmlsl2.i = call <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16> %vqdmlsl.i, <1 x i16> %vqdmlsl1.i)
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%0 = extractelement <1 x i32> %vqdmlsl2.i, i32 0
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ret i32 %0
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}
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define i64 @test_vqdmlsls_s32(i32 %a, i32 %b) {
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; CHECK: test_vqdmlsls_s32
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; CHECK: sqdmlsl {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vqdmlsl.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vqdmlsl1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vqdmlsl2.i = call <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32> %vqdmlsl.i, <1 x i32> %vqdmlsl1.i)
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%0 = extractelement <1 x i64> %vqdmlsl2.i, i32 0
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ret i64 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vqdmlsl.v1i32(<1 x i16>, <1 x i16>)
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declare <1 x i64> @llvm.aarch64.neon.vqdmlsl.v1i64(<1 x i32>, <1 x i32>)
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define i32 @test_vqdmullh_s16(i16 %a, i16 %b) {
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; CHECK: test_vqdmullh_s16
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; CHECK: sqdmull {{s[0-9]+}}, {{h[0-9]+}}, {{h[0-9]+}}
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entry:
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%vqdmull.i = insertelement <1 x i16> undef, i16 %a, i32 0
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%vqdmull1.i = insertelement <1 x i16> undef, i16 %b, i32 0
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%vqdmull2.i = call <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16> %vqdmull.i, <1 x i16> %vqdmull1.i)
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%0 = extractelement <1 x i32> %vqdmull2.i, i32 0
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ret i32 %0
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}
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define i64 @test_vqdmulls_s32(i32 %a, i32 %b) {
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; CHECK: test_vqdmulls_s32
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; CHECK: sqdmull {{d[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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entry:
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%vqdmull.i = insertelement <1 x i32> undef, i32 %a, i32 0
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%vqdmull1.i = insertelement <1 x i32> undef, i32 %b, i32 0
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%vqdmull2.i = call <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32> %vqdmull.i, <1 x i32> %vqdmull1.i)
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%0 = extractelement <1 x i64> %vqdmull2.i, i32 0
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ret i64 %0
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}
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declare <1 x i32> @llvm.aarch64.neon.vqdmull.v1i32(<1 x i16>, <1 x i16>)
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declare <1 x i64> @llvm.aarch64.neon.vqdmull.v1i64(<1 x i32>, <1 x i32>)
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@ -4460,3 +4460,45 @@
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: neg d29, s24
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Signed Saturating Doubling Multiply-Add Long
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//----------------------------------------------------------------------
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sqdmlal s17, h27, s12
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sqdmlal d19, s24, d12
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmlal s17, h27, s12
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmlal d19, s24, d12
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Signed Saturating Doubling Multiply-Subtract Long
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//----------------------------------------------------------------------
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sqdmlsl s14, h12, s25
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sqdmlsl d12, s23, d13
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmlsl s14, h12, s25
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmlsl d12, s23, d13
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// CHECK-ERROR: ^
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//----------------------------------------------------------------------
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// Signed Saturating Doubling Multiply Long
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//----------------------------------------------------------------------
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sqdmull s12, h22, s12
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sqdmull d15, s22, d12
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmull s12, h22, s12
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// CHECK-ERROR: ^
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// CHECK-ERROR: error: invalid operand for instruction
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// CHECK-ERROR: sqdmull d15, s22, d12
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// CHECK-ERROR: ^
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@ -31,3 +31,33 @@
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// CHECK: fmulx s20, s22, s15 // encoding: [0xd4,0xde,0x2f,0x5e]
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// CHECK: fmulx d23, d11, d1 // encoding: [0x77,0xdd,0x61,0x5e]
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//----------------------------------------------------------------------
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// Signed Saturating Doubling Multiply-Add Long
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//----------------------------------------------------------------------
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sqdmlal s17, h27, h12
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sqdmlal d19, s24, s12
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// CHECK: sqdmlal s17, h27, h12 // encoding: [0x71,0x93,0x6c,0x5e]
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// CHECK: sqdmlal d19, s24, s12 // encoding: [0x13,0x93,0xac,0x5e]
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//----------------------------------------------------------------------
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// Signed Saturating Doubling Multiply-Subtract Long
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//----------------------------------------------------------------------
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sqdmlsl s14, h12, h25
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sqdmlsl d12, s23, s13
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// CHECK: sqdmlsl s14, h12, h25 // encoding: [0x8e,0xb1,0x79,0x5e]
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// CHECK: sqdmlsl d12, s23, s13 // encoding: [0xec,0xb2,0xad,0x5e]
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//----------------------------------------------------------------------
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// Signed Saturating Doubling Multiply Long
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//----------------------------------------------------------------------
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sqdmull s12, h22, h12
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sqdmull d15, s22, s12
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// CHECK: sqdmull s12, h22, h12 // encoding: [0xcc,0xd2,0x6c,0x5e]
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// CHECK: sqdmull d15, s22, s12 // encoding: [0xcf,0xd2,0xac,0x5e]
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@ -1659,3 +1659,27 @@
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0xf4,0x39,0x60,0x7e
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0x95,0x39,0xa0,0x7e
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0xd2,0x3a,0xe0,0x7e
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#----------------------------------------------------------------------
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# Signed Saturating Doubling Multiply-Add Long
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#----------------------------------------------------------------------
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# CHECK: sqdmlal s17, h27, h12
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# CHECK: sqdmlal d19, s24, s12
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0x71,0x93,0x6c,0x5e
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0x13,0x93,0xac,0x5e
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#----------------------------------------------------------------------
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# Signed Saturating Doubling Multiply-Subtract Long
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#----------------------------------------------------------------------
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# CHECK: sqdmlsl s14, h12, h25
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# CHECK: sqdmlsl d12, s23, s13
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0x8e,0xb1,0x79,0x5e
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0xec,0xb2,0xad,0x5e
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#----------------------------------------------------------------------
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# Signed Saturating Doubling Multiply Long
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#----------------------------------------------------------------------
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# CHECK: sqdmull s12, h22, h12
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# CHECK: sqdmull d15, s22, s12
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0xcc,0xd2,0x6c,0x5e
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0xcf,0xd2,0xac,0x5e
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