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Add instruction encodings / disassembly support for l5r instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2013-01-25 20:20:07 +00:00
parent 0e3f426948
commit 3b6a5eefe0
4 changed files with 67 additions and 13 deletions
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39
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -175,6 +175,11 @@ static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -597,6 +602,40 @@ DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
static DecodeStatus
DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a L6R instruction.
Inst.clear();
unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
switch (Opcode) {
case 0x00:
Inst.setOpcode(XCore::LMUL_l6r);
return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
static DecodeStatus
DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3, Op4, Op5;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
return S;
}
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,

7
lib/Target/XCore/XCoreInstrFormats.td
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@ -222,8 +222,13 @@ class _L4R<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
}
class _L5R<dag outs, dag ins, string asmstr, list<dag> pattern>
class _FL5R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
: InstXCore<4, outs, ins, asmstr, pattern> {
let Inst{31-27} = opc{5-1};
let Inst{20} = opc{0};
let Inst{15-11} = 0b11111;
let DecoderMethod = "DecodeL5RInstruction";
}
class _FL6R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>

23
lib/Target/XCore/XCoreInstrInfo.td
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@ -485,19 +485,18 @@ def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2),
// Five operand long
def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"ladd $dst2, $dst1, $src1, $src2, $src3",
[]>;
def LSUB_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"lsub $dst2, $dst1, $src1, $src2, $src3",
[]>;
def LDIVU_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2),
def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
"ladd $dst2, $dst1, $src1, $src2, $src3",
[]>;
def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"lsub $dst2, $dst1, $src1, $src2, $src3", []>;
def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
// Six operand long

11
test/MC/Disassembler/XCore/xcore.txt
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@ -461,3 +461,14 @@
# CHECK: lmul r11, r0, r2, r5, r8, r10
0xf9 0xfa 0x02 0x06
# l5r instructions
# CHECK: ladd r10, r2, r5, r1, r7
0xe5 0xf8 0xfb 0x06
# CHECK: ldivu r5, r6, r3, r9, r8
0x54 0xfe 0x0b 0x07
# CHECK: lsub r1, r8, r7, r11, r5
0xcf 0xfd 0x85 0x0f