Add instruction encodings / disassembly support for l5r instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne
2013-01-25 20:20:07 +00:00
parent 0e3f426948
commit 3b6a5eefe0
4 changed files with 67 additions and 13 deletions

View File

@ -175,6 +175,11 @@ static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
#include "XCoreGenDisassemblerTables.inc"
static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
@ -597,6 +602,40 @@ DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return S;
}
static DecodeStatus
DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a L6R instruction.
Inst.clear();
unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
switch (Opcode) {
case 0x00:
Inst.setOpcode(XCore::LMUL_l6r);
return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
static DecodeStatus
DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2, Op3, Op4, Op5;
DecodeStatus S =
Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
if (S != MCDisassembler::Success)
return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
return S;
}
MCDisassembler::DecodeStatus
XCoreDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,