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https://github.com/c64scene-ar/llvm-6502.git
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Add instruction encodings / disassembly support for l5r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -175,6 +175,11 @@ static DecodeStatus DecodeL6RInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeL5RInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -597,6 +602,40 @@ DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeL5RInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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// Try and decode as a L6R instruction.
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Inst.clear();
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unsigned Opcode = fieldFromInstruction(Insn, 27, 5);
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switch (Opcode) {
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case 0x00:
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Inst.setOpcode(XCore::LMUL_l6r);
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return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
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}
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return MCDisassembler::Fail;
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}
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static DecodeStatus
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DecodeL5RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2, Op3, Op4, Op5;
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DecodeStatus S =
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Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
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if (S != MCDisassembler::Success)
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return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
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S = Decode2OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5);
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if (S != MCDisassembler::Success)
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return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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