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Add support for marking each operand as a %hh, %hm, %lm or %lo.

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Represent previous bools and these ones with flags in a single byte
per operand.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@2860 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vikram S. Adve 2002-07-10 21:45:04 +00:00
parent 6a49a1e321
commit 3bc9ef9317
1 changed files with 38 additions and 34 deletions
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72
lib/CodeGen/MachineInstr.cpp
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@ -49,9 +49,10 @@ MachineInstr::SetMachineOperandVal(unsigned int i,
{
assert(i < operands.size());
operands[i].Initialize(opType, _val);
operands[i].isDef = isdef ||
TargetInstrDescriptors[opCode].resultPos == (int) i;
operands[i].isDefAndUse = isDefAndUse;
if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
operands[i].markDef();
if (isDefAndUse)
operands[i].markDefAndUse();
}
void
@ -63,8 +64,6 @@ MachineInstr::SetMachineOperandConst(unsigned int i,
assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
"immed. constant cannot be defined");
operands[i].InitializeConst(operandType, intValue);
operands[i].isDef = false;
operands[i].isDefAndUse = false;
}
void
@ -76,9 +75,10 @@ MachineInstr::SetMachineOperandReg(unsigned int i,
{
assert(i < operands.size());
operands[i].InitializeReg(regNum, isCCReg);
operands[i].isDef = isdef ||
TargetInstrDescriptors[opCode].resultPos == (int) i;
operands[i].isDefAndUse = isDefAndUse;
if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
operands[i].markDef();
if (isDefAndUse)
operands[i].markDefAndUse();
regsUsed.insert(regNum);
}
@ -101,10 +101,9 @@ static inline std::ostream &OutputValue(std::ostream &os,
{
os << "(val ";
if (val && val->hasName())
return os << val->getName();
return os << val->getName() << ")";
else
return os << (void*) val; // print address only
os << ")";
return os << (void*) val << ")"; // print address only
}
std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
@ -134,38 +133,37 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
return os << "\n";
}
static inline std::ostream &OutputOperand(std::ostream &os,
const MachineOperand &mop)
{
Value* val;
switch (mop.getOperandType())
{
case MachineOperand::MO_CCRegister:
case MachineOperand::MO_VirtualRegister:
return OutputValue(os, mop.getVRegValue());
case MachineOperand::MO_MachineRegister:
return os << "(" << mop.getMachineRegNum() << ")";
default:
assert(0 && "Unknown operand type");
return os;
}
}
std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
{
if (mop.opHiBits32())
os << "%lm(";
else if (mop.opLoBits32())
os << "%lo(";
else if (mop.opHiBits64())
os << "%hh(";
else if (mop.opLoBits64())
os << "%hm(";
switch(mop.opType)
{
case MachineOperand::MO_VirtualRegister:
case MachineOperand::MO_MachineRegister:
os << "%reg";
return OutputOperand(os, mop);
OutputValue(os, mop.getVRegValue());
break;
case MachineOperand::MO_CCRegister:
os << "%ccreg";
return OutputOperand(os, mop);
OutputValue(os, mop.getVRegValue());
break;
case MachineOperand::MO_MachineRegister:
os << "%reg";
os << "(" << mop.getMachineRegNum() << ")";
break;
case MachineOperand::MO_SignExtendedImmed:
return os << (long)mop.immedVal;
os << (long)mop.immedVal;
break;
case MachineOperand::MO_UnextendedImmed:
return os << (long)mop.immedVal;
os << (long)mop.immedVal;
break;
case MachineOperand::MO_PCRelativeDisp:
{
const Value* opVal = mop.getVRegValue();
@ -175,12 +173,18 @@ std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
os << opVal->getName();
else
os << (const void*) opVal;
return os << ")";
os << ")";
break;
}
default:
assert(0 && "Unrecognized operand type");
break;
}
if (mop.flags &
(MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
os << ")";
return os;
}