mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-19 04:32:19 +00:00
fix expansion of ct[lt]z nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21896 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
39a8f33630
commit
3becf2026b
@ -2287,6 +2287,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
|
||||
case ISD::CTLZ: {
|
||||
// ctlz (HL) -> ctlz(H) != 32 ? ctlz(H) : (ctlz(L)+32)
|
||||
ExpandOp(Node->getOperand(0), Lo, Hi);
|
||||
SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
|
||||
SDOperand HLZ = DAG.getNode(ISD::CTLZ, NVT, Hi);
|
||||
SDOperand TopNotZero = DAG.getSetCC(ISD::SETNE, TLI.getSetCCResultTy(),
|
||||
@ -2301,6 +2302,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
|
||||
|
||||
case ISD::CTTZ: {
|
||||
// cttz (HL) -> cttz(L) != 32 ? cttz(L) : (cttz(H)+32)
|
||||
ExpandOp(Node->getOperand(0), Lo, Hi);
|
||||
SDOperand BitsC = DAG.getConstant(MVT::getSizeInBits(NVT), NVT);
|
||||
SDOperand LTZ = DAG.getNode(ISD::CTTZ, NVT, Lo);
|
||||
SDOperand BotNotZero = DAG.getSetCC(ISD::SETNE, TLI.getSetCCResultTy(),
|
||||
|
Loading…
x
Reference in New Issue
Block a user