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Target instruction selection should copy memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2050,8 +2050,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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SDValue Pred = getAL(CurDAG);
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SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
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SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
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return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other,
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Ops, 5);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
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SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl,
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MVT::v2f64, MVT::Other, Ops, 5);
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cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
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return Ret;
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}
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// Other cases are autogenerated.
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break;
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@ -2067,7 +2071,11 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
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SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
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SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
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AM5Opc, Pred, PredReg, Chain };
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return CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
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MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
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MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
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SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
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cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
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return Ret;
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}
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// Other cases are autogenerated.
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break;
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