mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-13 20:32:21 +00:00
Target instruction selection should copy memoperands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104110 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
9248b3208a
commit
3c3195cbf1
@ -2050,8 +2050,12 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
|
||||
SDValue Pred = getAL(CurDAG);
|
||||
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
|
||||
SDValue Ops[] = { N->getOperand(1), AM5Opc, Pred, PredReg, Chain };
|
||||
return CurDAG->getMachineNode(ARM::VLDMQ, dl, MVT::v2f64, MVT::Other,
|
||||
Ops, 5);
|
||||
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
||||
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
|
||||
SDNode *Ret = CurDAG->getMachineNode(ARM::VLDMQ, dl,
|
||||
MVT::v2f64, MVT::Other, Ops, 5);
|
||||
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
|
||||
return Ret;
|
||||
}
|
||||
// Other cases are autogenerated.
|
||||
break;
|
||||
@ -2067,7 +2071,11 @@ SDNode *ARMDAGToDAGISel::Select(SDNode *N) {
|
||||
SDValue PredReg = CurDAG->getRegister(0, MVT::i32);
|
||||
SDValue Ops[] = { N->getOperand(1), N->getOperand(2),
|
||||
AM5Opc, Pred, PredReg, Chain };
|
||||
return CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
|
||||
MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
|
||||
MemOp[0] = cast<MemSDNode>(N)->getMemOperand();
|
||||
SDNode *Ret = CurDAG->getMachineNode(ARM::VSTMQ, dl, MVT::Other, Ops, 6);
|
||||
cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1);
|
||||
return Ret;
|
||||
}
|
||||
// Other cases are autogenerated.
|
||||
break;
|
||||
|
Loading…
Reference in New Issue
Block a user