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Fix PR2986: do not use a potentially illegal

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type for the shift amount type.  Add a check
that shifts and rotates use the type returned
by getShiftAmountTy for the amount.  This
exposed some problems in CellSPU and PPC,
which have already been fixed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58455 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-10-30 20:26:50 +00:00
parent c9d4d755cf
commit 3d0f5afefb
1 changed files with 6 additions and 1 deletions
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7
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2390,6 +2390,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
"Shift operators return type must be the same as their first arg");
assert(VT.isInteger() && N2.getValueType().isInteger() &&
"Shifts only work on integers");
assert(N2.getValueType() == TLI.getShiftAmountTy() &&
"Wrong type for shift amount");
// Always fold shifts of i1 values so the code generator doesn't need to
// handle them. Since we know the size of the shift has to be less than the
@ -2763,12 +2765,15 @@ static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG) {
return DAG.getConstantFP(APFloat(Val), VT);
}
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
Value = DAG.getNode(ISD::ZERO_EXTEND, VT, Value);
unsigned Shift = 8;
for (unsigned i = NumBits; i > 8; i >>= 1) {
Value = DAG.getNode(ISD::OR, VT,
DAG.getNode(ISD::SHL, VT, Value,
DAG.getConstant(Shift, MVT::i8)), Value);
DAG.getConstant(Shift,
TLI.getShiftAmountTy())),
Value);
Shift <<= 1;
}