6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-12 13:30:51 +00:00
Code Issues Projects Releases Wiki Activity

srem doesn't actually have the same resulting sign as its numerator, you could

Browse Source 
also have a zero when numerator = denominator. Reverts parts of r126635 and
r126637.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nick Lewycky 2011-02-28 09:17:39 +00:00
parent b042f8e969
commit 3dc7e49c70
3 changed files with 5 additions and 37 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Analysis/ValueTracking.cpp
View File

@ -460,18 +460,6 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
}
}
if (Mask.isNegative()) { // We're looking for the sign bit.
APInt Mask2 = APInt::getSignBit(BitWidth);
KnownZero2 = 0;
KnownOne2 = 0;
ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD,
Depth+1);
if (KnownOne2[BitWidth-1])
KnownOne |= Mask2;
if (KnownZero2[BitWidth-1])
KnownZero |= Mask2;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
}
break;
case Instruction::URem: {
if (ConstantInt *Rem = dyn_cast<ConstantInt>(I->getOperand(1))) {

10
lib/Transforms/InstCombine/InstCombineCompares.cpp
View File

@ -1348,16 +1348,6 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
}
}
break;
case Instruction::SRem: {
bool TrueIfSigned;
if (LHSI->hasOneUse() &&
isSignBitCheck(ICI.getPredicate(), RHS, TrueIfSigned)) {
// srem has the same sign as its dividend so the divisor is irrelevant.
return new ICmpInst(ICI.getPredicate(), LHSI->getOperand(0), RHS);
}
break;
}
}
// Simplify icmp_eq and icmp_ne instructions with integer constant RHS.

20
test/Transforms/InstCombine/icmp.ll
View File

@ -378,28 +378,18 @@ define i1 @test38(i32 %x, i32 %y, i32 %z) {
ret i1 %c
}
; PR9343 #7
; CHECK: @test39
; CHECK: ret i1 false
define i1 @test39(i31 %X, i32 %Y) {
%A = zext i31 %X to i32
%B = srem i32 %A, %Y
%C = icmp slt i32 %B, 0
ret i1 %C
}
; PR9343 #1
; CHECK: test40
; CHECK: test39
; CHECK %B = icmp eq i32 %X, 0
define i1 @test40(i32 %X, i32 %Y) {
define i1 @test39(i32 %X, i32 %Y) {
%A = ashr exact i32 %X, %Y
%B = icmp eq i32 %A, 0
ret i1 %B
}
; CHECK: test41
; CHECK %B = icmp ne i32 %X, 0
define i1 @test41(i32 %X, i32 %Y) {
; CHECK: test40
; CHECK: %B = icmp ne i32 %X, 0
define i1 @test40(i32 %X, i32 %Y) {
%A = lshr exact i32 %X, %Y
%B = icmp ne i32 %A, 0
ret i1 %B