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Add support for parsing the XOR operator in Intel syntax inline assembly.
Differential Revision: http://reviews.llvm.org/D10385 Patch by marina.yatsina@intel.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239695 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,15 +42,16 @@ namespace {
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static const char OpPrecedence[] = {
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0, // IC_OR
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1, // IC_AND
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2, // IC_LSHIFT
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2, // IC_RSHIFT
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3, // IC_PLUS
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3, // IC_MINUS
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4, // IC_MULTIPLY
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4, // IC_DIVIDE
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5, // IC_RPAREN
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6, // IC_LPAREN
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1, // IC_XOR
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2, // IC_AND
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3, // IC_LSHIFT
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3, // IC_RSHIFT
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4, // IC_PLUS
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4, // IC_MINUS
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5, // IC_MULTIPLY
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5, // IC_DIVIDE
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6, // IC_RPAREN
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7, // IC_LPAREN
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0, // IC_IMM
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0 // IC_REGISTER
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};
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@ -70,6 +71,7 @@ private:
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enum InfixCalculatorTok {
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IC_OR = 0,
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IC_XOR,
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IC_AND,
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IC_LSHIFT,
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IC_RSHIFT,
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@ -204,6 +206,12 @@ private:
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Val = Op1.second | Op2.second;
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OperandStack.push_back(std::make_pair(IC_IMM, Val));
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break;
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case IC_XOR:
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assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
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"Xor operation with an immediate and a register!");
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Val = Op1.second ^ Op2.second;
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OperandStack.push_back(std::make_pair(IC_IMM, Val));
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break;
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case IC_AND:
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assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
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"And operation with an immediate and a register!");
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@ -232,6 +240,7 @@ private:
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enum IntelExprState {
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IES_OR,
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IES_XOR,
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IES_AND,
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IES_LSHIFT,
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IES_RSHIFT,
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@ -297,6 +306,21 @@ private:
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}
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PrevState = CurrState;
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}
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void onXor() {
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IntelExprState CurrState = State;
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switch (State) {
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default:
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State = IES_ERROR;
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break;
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case IES_INTEGER:
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case IES_RPAREN:
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case IES_REGISTER:
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State = IES_XOR;
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IC.pushOperator(IC_XOR);
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break;
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}
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PrevState = CurrState;
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}
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void onAnd() {
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IntelExprState CurrState = State;
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switch (State) {
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@ -473,6 +497,7 @@ private:
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case IES_MINUS:
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case IES_NOT:
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case IES_OR:
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case IES_XOR:
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case IES_AND:
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case IES_LSHIFT:
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case IES_RSHIFT:
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@ -496,7 +521,7 @@ private:
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PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
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PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
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PrevState == IES_LPAREN || PrevState == IES_LBRAC ||
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PrevState == IES_NOT) &&
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PrevState == IES_NOT || PrevState == IES_XOR) &&
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CurrState == IES_MINUS) {
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// Unary minus. No need to pop the minus operand because it was never
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// pushed.
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@ -506,7 +531,7 @@ private:
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PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
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PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
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PrevState == IES_LPAREN || PrevState == IES_LBRAC ||
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PrevState == IES_NOT) &&
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PrevState == IES_NOT || PrevState == IES_XOR) &&
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CurrState == IES_NOT) {
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// Unary not. No need to pop the not operand because it was never
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// pushed.
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@ -593,6 +618,7 @@ private:
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case IES_MINUS:
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case IES_NOT:
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case IES_OR:
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case IES_XOR:
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case IES_AND:
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case IES_LSHIFT:
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case IES_RSHIFT:
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@ -605,7 +631,7 @@ private:
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PrevState == IES_LSHIFT || PrevState == IES_RSHIFT ||
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PrevState == IES_MULTIPLY || PrevState == IES_DIVIDE ||
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PrevState == IES_LPAREN || PrevState == IES_LBRAC ||
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PrevState == IES_NOT) &&
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PrevState == IES_NOT || PrevState == IES_XOR) &&
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(CurrState == IES_MINUS || CurrState == IES_NOT)) {
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State = IES_ERROR;
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break;
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@ -1217,6 +1243,7 @@ bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
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case AsmToken::Star: SM.onStar(); break;
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case AsmToken::Slash: SM.onDivide(); break;
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case AsmToken::Pipe: SM.onOr(); break;
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case AsmToken::Caret: SM.onXor(); break;
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case AsmToken::Amp: SM.onAnd(); break;
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case AsmToken::LessLess:
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SM.onLShift(); break;
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@ -20,3 +20,5 @@
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add eax, 9876 >> 1
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// CHECK: addl $19752, %eax
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add eax, 9876 << 1
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// CHECK: addl $5, %eax
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add eax, 6 ^ 3
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