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[SystemZ] Allow 8-bit operands to RISBG

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RISBG has three 8-bit operands (I3, I4 and I5).  I'd originally
restricted all three to 6 bits, since that's the only range we intended
to use at the time.  However, the top bit of I4 acts as a "zero" flag for
RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co.
This patch therefore allows them to have the full 8-bit range.
I've left the fifth operand as a 6-bit value for now since the
upper 2 bits have no defined meaning.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186070 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-07-11 08:37:13 +00:00
parent c48b55a33d
commit 3ee0673e4f
4 changed files with 13 additions and 14 deletions
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3
lib/Target/SystemZ/SystemZInstrFormats.td
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@ -1020,8 +1020,7 @@ multiclass CmpSwapRSPair<string mnemonic, bits<8> rsOpcode, bits<16> rsyOpcode,
class RotateSelectRIEf<string mnemonic, bits<16> opcode, RegisterOperand cls1,
RegisterOperand cls2>
: InstRIEf<opcode, (outs cls1:$R1),
(ins cls1:$R1src, cls2:$R2,
uimm8zx6:$I3, uimm8zx6:$I4, uimm8zx6:$I5),
(ins cls1:$R1src, cls2:$R2, uimm8:$I3, uimm8:$I4, uimm8zx6:$I5),
mnemonic#"\t$R1, $R2, $I3, $I4, $I5", []> {
let Constraints = "$R1 = $R1src";
let DisableEncoding = "$R1src";

8
test/MC/Disassembler/SystemZ/insns.txt
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@ -4642,11 +4642,11 @@
# CHECK: risbg %r0, %r0, 0, 0, 63
0xec 0x00 0x00 0x00 0x3f 0x55
# CHECK: risbg %r0, %r0, 0, 63, 0
0xec 0x00 0x00 0x3f 0x00 0x55
# CHECK: risbg %r0, %r0, 0, 255, 0
0xec 0x00 0x00 0xff 0x00 0x55
# CHECK: risbg %r0, %r0, 63, 0, 0
0xec 0x00 0x3f 0x00 0x00 0x55
# CHECK: risbg %r0, %r0, 255, 0, 0
0xec 0x00 0xff 0x00 0x00 0x55
# CHECK: risbg %r0, %r15, 0, 0, 0
0xec 0x0f 0x00 0x00 0x00 0x55

8
test/MC/SystemZ/insn-bad.s
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@ -2102,18 +2102,18 @@
#CHECK: error: invalid operand
#CHECK: risbg %r0,%r0,0,-1,0
#CHECK: error: invalid operand
#CHECK: risbg %r0,%r0,0,64,0
#CHECK: risbg %r0,%r0,0,256,0
#CHECK: error: invalid operand
#CHECK: risbg %r0,%r0,-1,0,0
#CHECK: error: invalid operand
#CHECK: risbg %r0,%r0,64,0,0
#CHECK: risbg %r0,%r0,256,0,0
risbg %r0,%r0,0,0,-1
risbg %r0,%r0,0,0,64
risbg %r0,%r0,0,-1,0
risbg %r0,%r0,0,64,0
risbg %r0,%r0,0,256,0
risbg %r0,%r0,-1,0,0
risbg %r0,%r0,64,0,0
risbg %r0,%r0,256,0,0
#CHECK: error: invalid operand
#CHECK: rll %r0,%r0,-524289

8
test/MC/SystemZ/insn-good.s
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@ -5835,16 +5835,16 @@
#CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55]
#CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55]
#CHECK: risbg %r0, %r0, 0, 63, 0 # encoding: [0xec,0x00,0x00,0x3f,0x00,0x55]
#CHECK: risbg %r0, %r0, 63, 0, 0 # encoding: [0xec,0x00,0x3f,0x00,0x00,0x55]
#CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55]
#CHECK: risbg %r0, %r0, 255, 0, 0 # encoding: [0xec,0x00,0xff,0x00,0x00,0x55]
#CHECK: risbg %r0, %r15, 0, 0, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0x55]
#CHECK: risbg %r15, %r0, 0, 0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0x55]
#CHECK: risbg %r4, %r5, 6, 7, 8 # encoding: [0xec,0x45,0x06,0x07,0x08,0x55]
risbg %r0,%r0,0,0,0
risbg %r0,%r0,0,0,63
risbg %r0,%r0,0,63,0
risbg %r0,%r0,63,0,0
risbg %r0,%r0,0,255,0
risbg %r0,%r0,255,0,0
risbg %r0,%r15,0,0,0
risbg %r15,%r0,0,0,0
risbg %r4,%r5,6,7,8