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Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing more than one register simultaneously, specifically note functions that have spilled VRSAVE (currently, this can happen only in functions that use the setjmp intrinsic). As with CR spilling, such functions will need to provide two emergency spill slots to the scavenger. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -188,6 +188,11 @@ static bool spillsCR(const MachineFunction &MF) {
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return FuncInfo->isCRSpilled();
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}
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static bool spillsVRSAVE(const MachineFunction &MF) {
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const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
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return FuncInfo->isVRSAVESpilled();
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}
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static bool hasSpills(const MachineFunction &MF) {
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const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
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return FuncInfo->hasSpills();
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@ -1081,8 +1086,8 @@ PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
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// needed alignment padding.
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unsigned StackSize = determineFrameLayout(MF, false, true);
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MachineFrameInfo *MFI = MF.getFrameInfo();
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if (MFI->hasVarSizedObjects() || spillsCR(MF) || hasNonRISpills(MF) ||
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(hasSpills(MF) && !isInt<16>(StackSize))) {
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if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
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hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
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@ -440,7 +440,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI) const{
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bool &NonRI, bool &SpillsVRS) const{
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DebugLoc DL;
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if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
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@ -500,7 +500,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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Reg = PPC::CR7;
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return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
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&PPC::CRRCRegClass, NewMIs, NonRI);
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&PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
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} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX))
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@ -513,7 +513,7 @@ PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
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.addReg(SrcReg,
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getKillRegState(isKill)),
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FrameIdx));
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NonRI = true;
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SpillsVRS = true;
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} else {
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llvm_unreachable("Unknown regclass!");
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}
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@ -533,10 +533,14 @@ PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
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FuncInfo->setHasSpills();
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bool NonRI = false;
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if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs, NonRI))
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bool NonRI = false, SpillsVRS = false;
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if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs,
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NonRI, SpillsVRS))
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FuncInfo->setSpillsCR();
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if (SpillsVRS)
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FuncInfo->setSpillsVRSAVE();
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if (NonRI)
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FuncInfo->setHasNonRISpills();
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@ -557,7 +561,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI) const{
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bool &NonRI, bool &SpillsVRS) const{
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if (PPC::GPRCRegClass.hasSubClassEq(RC)) {
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if (DestReg != PPC::LR) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
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@ -616,7 +620,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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Reg = PPC::CR7;
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return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
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&PPC::CRRCRegClass, NewMIs, NonRI);
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&PPC::CRRCRegClass, NewMIs, NonRI, SpillsVRS);
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} else if (PPC::VRRCRegClass.hasSubClassEq(RC)) {
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NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LVX), DestReg),
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@ -627,7 +631,7 @@ PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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get(PPC::RESTORE_VRSAVE),
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DestReg),
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FrameIdx));
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NonRI = true;
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SpillsVRS = true;
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} else {
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llvm_unreachable("Unknown regclass!");
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}
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@ -649,10 +653,14 @@ PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
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FuncInfo->setHasSpills();
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bool NonRI = false;
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if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs, NonRI))
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bool NonRI = false, SpillsVRS = false;
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if (LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs,
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NonRI, SpillsVRS))
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FuncInfo->setSpillsCR();
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if (SpillsVRS)
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FuncInfo->setSpillsVRSAVE();
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if (NonRI)
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FuncInfo->setHasNonRISpills();
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@ -72,12 +72,12 @@ class PPCInstrInfo : public PPCGenInstrInfo {
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI) const;
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bool &NonRI, bool &SpillsVRS) const;
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bool LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs,
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bool &NonRI) const;
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bool &NonRI, bool &SpillsVRS) const;
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public:
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explicit PPCInstrInfo(PPCTargetMachine &TM);
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@ -47,6 +47,9 @@ class PPCFunctionInfo : public MachineFunctionInfo {
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/// SpillsCR - Indicates whether CR is spilled in the current function.
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bool SpillsCR;
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/// Indicates whether VRSAVE is spilled in the current function.
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bool SpillsVRSAVE;
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/// LRStoreRequired - The bool indicates whether there is some explicit use of
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/// the LR/LR8 stack slot that is not obvious from scanning the code. This
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/// requires that the code generator produce a store of LR to the stack on
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@ -88,6 +91,7 @@ public:
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HasSpills(false),
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HasNonRISpills(false),
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SpillsCR(false),
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SpillsVRSAVE(false),
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LRStoreRequired(false),
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MinReservedArea(0),
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TailCallSPDelta(0),
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@ -127,6 +131,9 @@ public:
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void setSpillsCR() { SpillsCR = true; }
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bool isCRSpilled() const { return SpillsCR; }
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void setSpillsVRSAVE() { SpillsVRSAVE = true; }
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bool isVRSAVESpilled() const { return SpillsVRSAVE; }
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void setLRStoreRequired() { LRStoreRequired = true; }
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bool isLRStoreRequired() const { return LRStoreRequired; }
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