Add support for fmul node of type v4f32.

void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  store <4 x float> %tmp2, <4 x float> *%a
  ret void
}

Is selected to:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v0, v0, v0, v1
        stvx v0, r2, r3
        blr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24701 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman 2005-12-14 00:34:09 +00:00
parent 993aeb2ed9
commit 3fb6877cb4
2 changed files with 21 additions and 0 deletions

View File

@ -602,6 +602,14 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr,
let Inst{21-31} = xo;
}
class VXForm_setzero<bits<11> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: VXForm_1<xo, OL, asmstr, itin, pattern> {
let VA = VD;
let VB = VD;
}
class VXForm_2<bits<11> xo, dag OL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<4, OL, asmstr, itin> {

View File

@ -897,6 +897,16 @@ def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB),
def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vsubfp $vD, $vA, $vB", VecFP,
[(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>;
def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
"vxor $vD, $vA, $vB", VecFP,
[]>;
// VX-Form Pseudo Instructions
def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
"vxor $vD, $vD, $vD", VecFP,
[]>;
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
@ -951,6 +961,9 @@ def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)),
def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)),
(ADDIS GPRC:$in, tconstpool:$g)>;
def : Pat<(fmul VRRC:$vA, VRRC:$vB),
(VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>;
// Fused multiply add and multiply sub for packed float. These are represented
// separately from the real instructions above, for operations that must have
// the additional precision, such as Newton-Rhapson (used by divide, sqrt)