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Enable EHABI by default

Browse Source 
After all hard work to implement the EHABI and with the test-suite
passing, it's time to turn it on by default and allow users to
disable it as a work-around while we fix the eventual bugs that show
up.

This commit also remove the -arm-enable-ehabi-descriptors, since we
want the tables to be printed every time the EHABI is turned on
for non-Darwin ARM targets.

Although MCJIT EHABI is not working yet (needs linking with the right
libraries), this commit also fixes some relocations on MCJIT regarding
the EH tables/lib calls, and update some tests to avoid using EH tables
when none are needed.

The EH tests in the test-suite that were previously disabled on ARM
now pass with these changes, so a follow-up commit on the test-suite
will re-enable them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200388 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Renato Golin 2014-01-29 11:50:56 +00:00
parent b04ddad8ea
commit 3fca788967
23 changed files with 64 additions and 59 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
lib/CodeGen/AsmPrinter/ARMException.cpp
View File

@ -36,12 +36,6 @@
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
static cl::opt<bool>
EnableARMEHABIDescriptors("arm-enable-ehabi-descriptors", cl::Hidden,
cl::desc("Generate ARM EHABI tables with unwinding descriptors"),
cl::init(false));
ARMException::ARMException(AsmPrinter *A)
: DwarfException(A) {}
@ -74,25 +68,23 @@ void ARMException::endFunction(const MachineFunction *) {
Asm->OutStreamer.EmitLabel(Asm->GetTempSymbol("eh_func_end",
Asm->getFunctionNumber()));
if (EnableARMEHABIDescriptors) {
// Map all labels and get rid of any dead landing pads.
MMI->TidyLandingPads();
// Map all labels and get rid of any dead landing pads.
MMI->TidyLandingPads();
if (!MMI->getLandingPads().empty()) {
// Emit references to personality.
if (const Function * Personality =
MMI->getPersonalities()[MMI->getPersonalityIndex()]) {
MCSymbol *PerSym = Asm->getSymbol(Personality);
Asm->OutStreamer.EmitSymbolAttribute(PerSym, MCSA_Global);
ATS.emitPersonality(PerSym);
}
// Emit .handlerdata directive.
ATS.emitHandlerData();
// Emit actual exception table
EmitExceptionTable();
if (!MMI->getLandingPads().empty()) {
// Emit references to personality.
if (const Function * Personality =
MMI->getPersonalities()[MMI->getPersonalityIndex()]) {
MCSymbol *PerSym = Asm->getSymbol(Personality);
Asm->OutStreamer.EmitSymbolAttribute(PerSym, MCSA_Global);
ATS.emitPersonality(PerSym);
}
// Emit .handlerdata directive.
ATS.emitHandlerData();
// Emit actual exception table
EmitExceptionTable();
}
}

3
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
View File

@ -481,8 +481,11 @@ void RuntimeDyldELF::resolveARMRelocation(const SectionEntry &Section,
default:
llvm_unreachable("Not implemented relocation type!");
case ELF::R_ARM_NONE:
break;
// Write a 32bit value to relocation address, taking into account the
// implicit addend encoded in the target.
case ELF::R_ARM_PREL31:
case ELF::R_ARM_TARGET1:
case ELF::R_ARM_ABS32:
*TargetPtr = *Placeholder + Value;

5
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -1106,7 +1106,7 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
}
}
extern cl::opt<bool> EnableARMEHABI;
extern cl::opt<bool> DisableARMEHABI;
// Simple pseudo-instructions have their lowering (with expansion to real
// instructions) auto-generated.
@ -1122,7 +1122,8 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
}
// Emit unwinding stuff for frame-related instructions
if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
if (Subtarget->isTargetEHABICompatible() && !DisableARMEHABI &&
MI->getFlag(MachineInstr::FrameSetup))
EmitUnwindingInstruction(MI);
// Do any auto-generated pseudo lowerings.

10
lib/Target/ARM/ARMSubtarget.h
View File

@ -328,6 +328,16 @@ public:
!isTargetDarwin();
}
// ARM Targets that support EHABI exception handling standard
// Darwin uses SjLj. Other targets might need more checks.
bool isTargetEHABICompatible() const {
return (TargetTriple.getEnvironment() == Triple::EABI ||
TargetTriple.getEnvironment() == Triple::GNUEABI ||
TargetTriple.getEnvironment() == Triple::EABIHF ||
TargetTriple.getEnvironment() == Triple::GNUEABIHF) &&
!isTargetDarwin();
}
bool isTargetHardFloat() const {
return TargetTriple.getEnvironment() == Triple::GNUEABIHF ||
TargetTriple.getEnvironment() == Triple::EABIHF;

8
lib/Target/ARM/MCTargetDesc/ARMMCAsmInfo.cpp
View File

@ -16,9 +16,11 @@
using namespace llvm;
// ARM EHABI is experimental but the quality is good enough
// to be turned on by default on non-Darwin ARM targets.
cl::opt<bool>
EnableARMEHABI("arm-enable-ehabi", cl::Hidden,
cl::desc("Generate ARM EHABI tables"),
DisableARMEHABI("arm-disable-ehabi", cl::Hidden,
cl::desc("Disable ARM experimental exception handling"),
cl::init(false));
@ -52,7 +54,7 @@ ARMELFMCAsmInfo::ARMELFMCAsmInfo() {
SupportsDebugInformation = true;
// Exceptions handling
if (EnableARMEHABI)
if (!DisableARMEHABI)
ExceptionsType = ExceptionHandling::ARM;
// foo(plt) instead of foo@plt

2
test/CodeGen/ARM/arm-ttype-target2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple=armv7-none-linux-gnueabi -arm-enable-ehabi -arm-enable-ehabi-descriptors < %s | FileCheck %s
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
@_ZTVN10__cxxabiv117__class_type_infoE = external global i8*
@_ZTS3Foo = linkonce_odr constant [5 x i8] c"3Foo\00"

2
test/CodeGen/ARM/ehabi-filters.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -arm-enable-ehabi -arm-enable-ehabi-descriptors < %s | FileCheck %s
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-none-linux-gnueabi"

3
test/CodeGen/ARM/ehabi-no-landingpad.ll
View File

@ -1,5 +1,4 @@
; RUN: llc < %s -mtriple=armv7-unknown-linux-gnueabi \
; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors | FileCheck %s
; RUN: llc < %s -mtriple=armv7-unknown-linux-gnueabi | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
target triple = "armv7-unknown-linux-gnueabi"

5
test/CodeGen/ARM/ehabi-unwind.ll
View File

@ -1,8 +1,7 @@
; Test that the EHABI unwind instruction generator does not encounter any
; unfamiliar instructions.
; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi -disable-fp-elim
; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi
; RUN: llc < %s -mtriple=thumbv7 -arm-enable-ehabi -arm-enable-ehabi-descriptors
; RUN: llc < %s -mtriple=thumbv7 -disable-fp-elim
; RUN: llc < %s -mtriple=thumbv7
define void @_Z1fv() nounwind {
entry:

4
test/CodeGen/ARM/ehabi.ll
View File

@ -19,22 +19,18 @@
; (4) armv7 without -disable-fp-elim
; RUN: llc -mtriple arm-unknown-linux-gnueabi \
; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \
; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP
; RUN: llc -mtriple arm-unknown-linux-gnueabi \
; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \
; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-FP-ELIM
; RUN: llc -mtriple armv7-unknown-linux-gnueabi \
; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \
; RUN: -disable-fp-elim -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP
; RUN: llc -mtriple armv7-unknown-linux-gnueabi \
; RUN: -arm-enable-ehabi -arm-enable-ehabi-descriptors \
; RUN: -filetype=asm -o - %s \
; RUN: | FileCheck %s --check-prefix=CHECK-V7-FP-ELIM

2
test/CodeGen/ARM/setcc-sentinals.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s
; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false -arm-disable-ehabi | FileCheck %s
define zeroext i1 @test0(i32 %x) nounwind {
; CHECK-LABEL: test0:

8
test/CodeGen/Thumb2/constant-islands.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -O0 -filetype=obj -o %t.o
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 -O0 -filetype=obj -o %t.o
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -O2 -filetype=obj -verify-machineinstrs -o %t.o
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 -O2 -filetype=obj -verify-machineinstrs -o %t.o
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -O0 -filetype=obj -o %t.o -arm-disable-ehabi
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 -O0 -filetype=obj -o %t.o -arm-disable-ehabi
; RUN: llc < %s -march=arm -mcpu=cortex-a8 -O2 -filetype=obj -verify-machineinstrs -o %t.o -arm-disable-ehabi
; RUN: llc < %s -march=thumb -mcpu=cortex-a8 -O2 -filetype=obj -verify-machineinstrs -o %t.o -arm-disable-ehabi
target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32"
target triple = "thumbv7-apple-ios"

2
test/ExecutionEngine/MCJIT/remote/Inputs/cross-module-b.ll
View File

@ -1,6 +1,6 @@
declare i32 @FA()
define i32 @FB() {
define i32 @FB() nounwind {
%r = call i32 @FA( ) ; <i32> [#uses=1]
ret i32 %r
}

2
test/ExecutionEngine/MCJIT/remote/Inputs/multi-module-b.ll
View File

@ -1,6 +1,6 @@
declare i32 @FC()
define i32 @FB() {
define i32 @FB() nounwind {
%r = call i32 @FC( ) ; <i32> [#uses=1]
ret i32 %r
}

2
test/ExecutionEngine/MCJIT/remote/Inputs/multi-module-c.ll
View File

@ -1,4 +1,4 @@
define i32 @FC() {
define i32 @FC() nounwind {
ret i32 0
}

5
test/ExecutionEngine/MCJIT/remote/cross-module-a.ll
View File

@ -2,12 +2,11 @@
declare i32 @FB()
define i32 @FA() {
define i32 @FA() nounwind {
ret i32 0
}
define i32 @main() {
define i32 @main() nounwind {
%r = call i32 @FB( ) ; <i32> [#uses=1]
ret i32 %r
}

2
test/ExecutionEngine/MCJIT/remote/multi-module-a.ll
View File

@ -2,7 +2,7 @@
declare i32 @FB()
define i32 @main() {
define i32 @main() nounwind {
%r = call i32 @FB( ) ; <i32> [#uses=1]
ret i32 %r
}

4
test/ExecutionEngine/MCJIT/remote/simpletest-remote.ll
View File

@ -1,10 +1,10 @@
; RUN: %lli_mcjit -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
define i32 @bar() {
define i32 @bar() nounwind {
ret i32 0
}
define i32 @main() {
define i32 @main() nounwind {
%r = call i32 @bar( ) ; <i32> [#uses=1]
ret i32 %r
}

2
test/ExecutionEngine/MCJIT/remote/test-data-align-remote.ll
View File

@ -3,7 +3,7 @@
; Check that a variable is always aligned as specified.
@var = global i32 0, align 32
define i32 @main() {
define i32 @main() nounwind {
%addr = ptrtoint i32* @var to i64
%mask = and i64 %addr, 31
%tst = icmp eq i64 %mask, 0

4
test/ExecutionEngine/MCJIT/remote/test-fp-no-external-funcs-remote.ll
View File

@ -1,6 +1,6 @@
; RUN: %lli_mcjit -remote-mcjit -mcjit-remote-process=lli-child-target%exeext %s > /dev/null
define double @test(double* %DP, double %Arg) {
define double @test(double* %DP, double %Arg) nounwind {
%D = load double* %DP ; <double> [#uses=1]
%V = fadd double %D, 1.000000e+00 ; <double> [#uses=2]
%W = fsub double %V, %V ; <double> [#uses=3]
@ -12,7 +12,7 @@ define double @test(double* %DP, double %Arg) {
ret double %Y
}
define i32 @main() {
define i32 @main() nounwind {
%X = alloca double ; <double*> [#uses=2]
store double 0.000000e+00, double* %X
call double @test( double* %X, double 2.000000e+00 ) ; <double>:1 [#uses=0]

2
test/ExecutionEngine/MCJIT/remote/test-global-init-nonzero-remote.ll
View File

@ -2,7 +2,7 @@
@count = global i32 1, align 4
define i32 @main() nounwind uwtable {
define i32 @main() nounwind {
entry:
%retval = alloca i32, align 4
%i = alloca i32, align 4

4
test/MC/ARM/data-in-code.ll
View File

@ -1,8 +1,8 @@
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -arm-disable-ehabi \
;; RUN: -mtriple=armv7-linux-gnueabi -filetype=obj %s -o - | \
;; RUN: llvm-readobj -t | FileCheck -check-prefix=ARM %s
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort \
;; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort -arm-disable-ehabi \
;; RUN: -mtriple=thumbv7-linux-gnueabi -filetype=obj %s -o - | \
;; RUN: llvm-readobj -t | FileCheck -check-prefix=TMB %s

4
test/MC/ARM/elf-thumbfunc-reloc.ll
View File

@ -32,6 +32,10 @@ entry:
; CHECK-NEXT: Section (2) .rel.text {
; CHECK-NEXT: 0x8 R_ARM_THM_CALL foo 0x0
; CHECK-NEXT: }
; CHECK-NEXT: Section (7) .rel.ARM.exidx {
; CHECK-NEXT: 0x0 R_ARM_PREL31 .text 0x0
; CHECK-NEXT: 0x8 R_ARM_PREL31 .text 0x0
; CHECK-NEXT: }
; CHECK-NEXT: ]
; make sure foo is thumb function: bit 0 = 1