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Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. It

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needs to demand the high bits because it's asserting that they're zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105406 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2010-06-03 20:21:33 +00:00
parent 3844173f6e
commit 400f75cb5e
2 changed files with 30 additions and 4 deletions
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12
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@@ -1498,13 +1498,17 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
break;
}
case ISD::AssertZext: {
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
// Demand all the bits of the input that are demanded in the output.
// The low bits are obvious; the high bits are demanded because we're
// asserting that they're zero here.
if (SimplifyDemandedBits(Op.getOperand(0), NewMask,
KnownZero, KnownOne, TLO, Depth+1))
return true;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
KnownZero |= ~InMask & NewMask;
break;
}