6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-21 02:29:22 +00:00
Code Issues Projects Releases Wiki Activity

mi-sched: bypass heuristic checks when regpressure tracking is disabled.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189988 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-09-04 21:00:02 +00:00
parent 42ebb3ad41
commit 40b52bb8f2
3 changed files with 35 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
include/llvm/CodeGen/MachineScheduler.h
View File

@ -271,6 +271,9 @@ public:
virtual ~ScheduleDAGMI();
/// Return true if register pressure tracking is enabled.
bool shouldTrackPressure() const { return ShouldTrackPressure; }
/// Add a postprocessing step to the DAG builder.
/// Mutations are applied in the order that they are added after normal DAG
/// building and before MachineSchedStrategy initialization.

53
lib/CodeGen/MachineScheduler.cpp
View File

@ -2363,30 +2363,32 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
const RegPressureTracker &RPTracker,
RegPressureTracker &TempTracker) {
// Always initialize TryCand's RPDelta.
if (Zone.isTop()) {
TempTracker.getMaxDownwardPressureDelta(
TryCand.SU->getInstr(),
TryCand.RPDelta,
DAG->getRegionCriticalPSets(),
DAG->getRegPressure().MaxSetPressure);
}
else {
if (VerifyScheduling) {
TempTracker.getMaxUpwardPressureDelta(
if (DAG->shouldTrackPressure()) {
// Always initialize TryCand's RPDelta.
if (Zone.isTop()) {
TempTracker.getMaxDownwardPressureDelta(
TryCand.SU->getInstr(),
&DAG->getPressureDiff(TryCand.SU),
TryCand.RPDelta,
DAG->getRegionCriticalPSets(),
DAG->getRegPressure().MaxSetPressure);
}
else {
RPTracker.getUpwardPressureDelta(
TryCand.SU->getInstr(),
DAG->getPressureDiff(TryCand.SU),
TryCand.RPDelta,
DAG->getRegionCriticalPSets(),
DAG->getRegPressure().MaxSetPressure);
if (VerifyScheduling) {
TempTracker.getMaxUpwardPressureDelta(
TryCand.SU->getInstr(),
&DAG->getPressureDiff(TryCand.SU),
TryCand.RPDelta,
DAG->getRegionCriticalPSets(),
DAG->getRegPressure().MaxSetPressure);
}
else {
RPTracker.getUpwardPressureDelta(
TryCand.SU->getInstr(),
DAG->getPressureDiff(TryCand.SU),
TryCand.RPDelta,
DAG->getRegionCriticalPSets(),
DAG->getRegPressure().MaxSetPressure);
}
}
}
@ -2403,8 +2405,9 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
// Avoid exceeding the target's limit. If signed PSetID is negative, it is
// invalid; convert it to INT_MAX to give it lowest priority.
if (tryPressure(TryCand.RPDelta.Excess, Cand.RPDelta.Excess, TryCand, Cand,
RegExcess))
if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.Excess,
Cand.RPDelta.Excess,
TryCand, Cand, RegExcess))
return;
// For loops that are acyclic path limited, aggressively schedule for latency.
@ -2412,8 +2415,9 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
return;
// Avoid increasing the max critical pressure in the scheduled region.
if (tryPressure(TryCand.RPDelta.CriticalMax, Cand.RPDelta.CriticalMax,
TryCand, Cand, RegCritical))
if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.CriticalMax,
Cand.RPDelta.CriticalMax,
TryCand, Cand, RegCritical))
return;
// Keep clustered nodes together to encourage downstream peephole
@ -2435,8 +2439,9 @@ void ConvergingScheduler::tryCandidate(SchedCandidate &Cand,
return;
}
// Avoid increasing the max pressure of the entire region.
if (tryPressure(TryCand.RPDelta.CurrentMax, Cand.RPDelta.CurrentMax,
TryCand, Cand, RegMax))
if (DAG->shouldTrackPressure() && tryPressure(TryCand.RPDelta.CurrentMax,
Cand.RPDelta.CurrentMax,
TryCand, Cand, RegMax))
return;
// Avoid critical resource consumption and balance the schedule.

6
lib/CodeGen/ScheduleDAGInstrs.cpp
View File

@ -185,9 +185,6 @@ void ScheduleDAGInstrs::enterRegion(MachineBasicBlock *bb,
RegionBegin = begin;
RegionEnd = end;
NumRegionInstrs = regioninstrs;
MISUnitMap.clear();
ScheduleDAG::clearDAG();
}
/// Close the current scheduling region. Don't clear any state in case the
@ -703,6 +700,9 @@ void ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA,
: ST.useAA();
AliasAnalysis *AAForDep = UseAA ? AA : 0;
MISUnitMap.clear();
ScheduleDAG::clearDAG();
// Create an SUnit for each real instruction.
initSUnits();