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Translate llvm target registers to dwarf register numbers properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27180 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -362,7 +362,7 @@ void AlphaRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
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// FIXME - Needs to handle register variables.
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// FIXME - Faking that llvm number is same as gcc numbering.
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ML.set((FP ? Alpha::R15 : Alpha::R30) - Alpha::R0,
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ML.set(getDwarfRegNum(FP ? Alpha::R15 : Alpha::R30),
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MFI->getObjectOffset(Index) + MFI->getStackSize());
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}
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@ -337,7 +337,7 @@ void IA64RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
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// FIXME - Needs to handle register variables.
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// FIXME - Faking that llvm number is same as gcc numbering.
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ML.set((FP ? IA64::r5 : IA64::r12) - IA64::r0,
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ML.set(getDwarfRegNum(FP ? IA64::r5 : IA64::r12),
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MFI->getObjectOffset(Index) + MFI->getStackSize());
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}
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@ -454,7 +454,7 @@ void PPCRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
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// FIXME - Needs to handle register variables.
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// FIXME - Faking that llvm number is same as gcc numbering.
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ML.set((FP ? PPC::R31 : PPC::R1) - PPC::R0,
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ML.set(getDwarfRegNum(FP ? PPC::R31 : PPC::R1),
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MFI->getObjectOffset(Index) + MFI->getStackSize());
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}
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@ -207,7 +207,7 @@ void SparcRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
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// FIXME - Needs to handle register variables.
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// FIXME - Faking that llvm number is same as gcc numbering.
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ML.set(SP::G1 - SP::G0,
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ML.set(getDwarfRegNum(SP::G1),
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MFI->getObjectOffset(Index) + MFI->getStackSize());
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}
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@ -693,7 +693,7 @@ void X86RegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
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// FIXME - Needs to handle register variables.
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// FIXME - Hardcoding gcc numbering.
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ML.set(FP ? 6 : 7,
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ML.set(getDwarfRegNum(FP ? X86::EBP : X86::ESP),
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MFI->getObjectOffset(Index) + MFI->getStackSize());
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}
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