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https://github.com/c64scene-ar/llvm-6502.git
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Don't use additional arguments for dss and friends to satisfy DSS_Form,
when let can do the same thing. Keep the 64bit variants as codegen-only. While they have a different register class, the encoding is the same for 32bit and 64bit mode. Having both present would otherwise confuse the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@214636 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Joerg Sonnenberger
parent
e411c38de9
commit
419f3804f0
@ -258,48 +258,64 @@ class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
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def HasAltivec : Predicate<"PPCSubTarget->hasAltivec()">;
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let Predicates = [HasAltivec] in {
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let isCodeGenOnly = 1 in {
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def DSS : DSS_Form<822, (outs),
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(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
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"dss $STRM", IIC_LdStLoad /*FIXME*/, []>,
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Deprecated<DeprecatedDST>;
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def DSSALL : DSS_Form<822, (outs),
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(ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
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"dssall", IIC_LdStLoad /*FIXME*/, []>,
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Deprecated<DeprecatedDST>;
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def DST : DSS_Form<342, (outs),
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(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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Deprecated<DeprecatedDST>;
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def DSTT : DSS_Form<342, (outs),
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(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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Deprecated<DeprecatedDST>;
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def DSTST : DSS_Form<374, (outs),
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(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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Deprecated<DeprecatedDST>;
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def DSTSTT : DSS_Form<374, (outs),
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(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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def DSS : DSS_Form<0, 822, (outs), (ins u5imm:$STRM),
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"dss $STRM", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dss imm:$STRM)]>,
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Deprecated<DeprecatedDST> {
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let A = 0;
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let B = 0;
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}
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def DSSALL : DSS_Form<1, 822, (outs), (ins),
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"dssall", IIC_LdStLoad /*FIXME*/, [(int_ppc_altivec_dssall)]>,
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Deprecated<DeprecatedDST> {
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let STRM = 0;
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let A = 0;
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let B = 0;
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}
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def DST : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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def DST64 : DSS_Form<342, (outs),
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(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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def DSTT : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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def DSTT64 : DSS_Form<342, (outs),
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(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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def DSTST : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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def DSTST64 : DSS_Form<374, (outs),
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(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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Deprecated<DeprecatedDST>;
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def DSTSTT64 : DSS_Form<374, (outs),
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(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
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def DSTSTT : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, gprc:$rA, gprc:$rB),
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"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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let isCodeGenOnly = 1 in {
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// The very same instructions as above, but formally matching 64bit registers.
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def DST64 : DSS_Form<0, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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def DSTT64 : DSS_Form<1, 342, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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def DSTST64 : DSS_Form<0, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dstst i64:$rA, i32:$rB,
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imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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def DSTSTT64 : DSS_Form<1, 374, (outs), (ins u5imm:$STRM, g8rc:$rA, gprc:$rB),
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"dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/,
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[(int_ppc_altivec_dststt i64:$rA, i32:$rB,
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imm:$STRM)]>,
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Deprecated<DeprecatedDST>;
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}
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def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
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@ -747,30 +763,6 @@ def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
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// Additional Altivec Patterns
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//
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// DS* intrinsics
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def : Pat<(int_ppc_altivec_dssall), (DSSALL 1, 0, 0, 0)>;
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def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>;
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// * 32-bit
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def : Pat<(int_ppc_altivec_dst i32:$rA, i32:$rB, imm:$STRM),
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(DST 0, imm:$STRM, $rA, $rB)>;
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def : Pat<(int_ppc_altivec_dstt i32:$rA, i32:$rB, imm:$STRM),
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(DSTT 1, imm:$STRM, $rA, $rB)>;
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def : Pat<(int_ppc_altivec_dstst i32:$rA, i32:$rB, imm:$STRM),
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(DSTST 0, imm:$STRM, $rA, $rB)>;
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def : Pat<(int_ppc_altivec_dststt i32:$rA, i32:$rB, imm:$STRM),
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(DSTSTT 1, imm:$STRM, $rA, $rB)>;
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// * 64-bit
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def : Pat<(int_ppc_altivec_dst i64:$rA, i32:$rB, imm:$STRM),
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(DST64 0, imm:$STRM, $rA, $rB)>;
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def : Pat<(int_ppc_altivec_dstt i64:$rA, i32:$rB, imm:$STRM),
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(DSTT64 1, imm:$STRM, $rA, $rB)>;
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def : Pat<(int_ppc_altivec_dstst i64:$rA, i32:$rB, imm:$STRM),
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(DSTST64 0, imm:$STRM, $rA, $rB)>;
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def : Pat<(int_ppc_altivec_dststt i64:$rA, i32:$rB, imm:$STRM),
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(DSTSTT64 1, imm:$STRM, $rA, $rB)>;
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// Loads.
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def : Pat<(v4i32 (load xoaddr:$src)), (LVX xoaddr:$src)>;
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@ -800,10 +800,9 @@ class DCB_Form<bits<10> xo, bits<5> immfield, dag OOL, dag IOL, string asmstr,
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// DSS_Form - Form X instruction, used for altivec dss* instructions.
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class DSS_Form<bits<10> xo, dag OOL, dag IOL, string asmstr,
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class DSS_Form<bits<1> T, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<31, OOL, IOL, asmstr, itin> {
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bits<1> T;
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bits<2> STRM;
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bits<5> A;
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bits<5> B;
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@ -2255,3 +2255,16 @@
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0x4c 0x00 0x00 0x4e
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# CHECK: rfmci
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0x4c 0x00 0x00 0x4c
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# CHECK: dss 3
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0x7c 0x60 0x06 0x6c
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# CHECK: dssall
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0x7e 0x00 0x06 0x6c
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# CHECK: dst 12, 11, 3
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0x7c 0x6c 0x5a 0xac
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# CHECK: dstt 12, 11, 3
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0x7e 0x6c 0x5a 0xac
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# CHECK: dstst 12, 11, 3
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0x7c 0x6c 0x5a 0xec
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# CHECK: dststt 12, 11, 3
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0x7e 0x6c 0x5a 0xec
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@ -3593,3 +3593,23 @@
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# CHECK-BE: rfmci # encoding: [0x4c,0x00,0x00,0x4c]
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# CHECK-LE: rfmci # encoding: [0x4c,0x00,0x00,0x4c]
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rfmci
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# Altivec Data Stream instruction:
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# CHECK-BE: dss 3 # encoding: [0x7c,0x60,0x06,0x6c]
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# CHECK-LE: dss 3 # encoding: [0x6c,0x06,0x60,0x7c]
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dss 3
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# CHECK-BE: dssall # encoding: [0x7e,0x00,0x06,0x6c]
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# CHECK-LE: dssall # encoding: [0x6c,0x06,0x00,0x7e]
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dssall
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# CHECK-BE: dst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xac]
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# CHECK-LE: dst 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7c]
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dst %r12, %r11, 3
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# CHECK-BE: dstt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xac]
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# CHECK-LE: dstt 12, 11, 3 # encoding: [0xac,0x5a,0x6c,0x7e]
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dstt %r12, %r11, 3
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# CHECK-BE: dstst 12, 11, 3 # encoding: [0x7c,0x6c,0x5a,0xec]
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# CHECK-LE: dstst 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7c]
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dstst %r12, %r11, 3
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# CHECK-BE: dststt 12, 11, 3 # encoding: [0x7e,0x6c,0x5a,0xec]
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# CHECK-LE: dststt 12, 11, 3 # encoding: [0xec,0x5a,0x6c,0x7e]
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dststt %r12, %r11, 3
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