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Updates to match change of getRegForInlineAsmConstraint prototype

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-21 23:11:00 +00:00
parent aba3b13fb3
commit 4217ca8dc1
5 changed files with 12 additions and 7 deletions
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3
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -745,7 +745,8 @@ bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
std::vector<unsigned> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint) const {
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
// Not a physreg, must not be a register reference or something.
if (Constraint[0] != '{') return std::vector<unsigned>();
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");

5
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -999,7 +999,8 @@ PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
std::vector<unsigned> PPCTargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint) const {
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
if (Constraint.size() == 1) {
switch (Constraint[0]) { // GCC RS6000 Constraint Letters
default: break; // Unknown constriant letter
@ -1051,7 +1052,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint) const {
}
// Handle explicit register names.
return TargetLowering::getRegForInlineAsmConstraint(Constraint);
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}
// isOperandValidForConstraint

3
lib/Target/PowerPC/PPCISelLowering.h
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@ -99,7 +99,8 @@ namespace llvm {
ConstraintType getConstraintType(char ConstraintLetter) const;
std::vector<unsigned>
getRegForInlineAsmConstraint(const std::string &Constraint) const;
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
};
}

5
lib/Target/X86/X86ISelLowering.cpp
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@ -1961,7 +1961,8 @@ void X86TargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
}
std::vector<unsigned> X86TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint) const {
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const {
if (Constraint.size() == 1) {
// FIXME: not handling fp-stack yet!
// FIXME: not handling MMX registers yet ('y' constraint).
@ -1993,5 +1994,5 @@ getRegForInlineAsmConstraint(const std::string &Constraint) const {
}
// Handle explicit register names.
return TargetLowering::getRegForInlineAsmConstraint(Constraint);
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
}

3
lib/Target/X86/X86ISelLowering.h
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@ -224,7 +224,8 @@ namespace llvm {
SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
std::vector<unsigned>
getRegForInlineAsmConstraint(const std::string &Constraint) const;
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT::ValueType VT) const;
private:
// C Calling Convention implementation.
std::vector<SDOperand> LowerCCCArguments(Function &F, SelectionDAG &DAG);