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Mark tBX as an indirect branch rather than a return.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132107 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1863,7 +1863,7 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tBX_RET_vararg);
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TmpInst.setOpcode(ARM::tBX);
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TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
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// Predicate.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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@ -361,14 +361,6 @@ def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
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//
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let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
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T1Special<{1,1,0,?}> {
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// A6.2.3 & A8.6.25
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bits<4> Rm;
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let Inst{6-3} = Rm;
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let Inst{2-0} = 0b000;
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}
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def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
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[(ARMretflag)]>,
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T1Special<{1,1,0,?}> {
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@ -391,6 +383,14 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
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T1Special<{1,1,0,?}> {
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// A6.2.3 & A8.6.25
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bits<4> Rm;
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let Inst{6-3} = Rm;
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let Inst{2-0} = 0b000;
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}
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def tBRIND : TI<(outs), (ins GPR:$Rm),
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IIC_Br,
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"mov\tpc, $Rm",
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