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Fix X86 codegen for 'atomicrmw nand' to generate *x = ~(*x & y), not *x = ~*x & y.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154705 91177308-0d34-0410-b5e6-96231b3b80d8
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Richard Smith committed
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@@ -11298,14 +11298,15 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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unsigned notOpc,
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unsigned EAXreg,
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const TargetRegisterClass *RC,
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bool invSrc) const {
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bool Invert) const {
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// For the atomic bitwise operator, we generate
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// thisMBB:
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// newMBB:
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// ld t1 = [bitinstr.addr]
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// op t2 = t1, [bitinstr.val]
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// not t3 = t2 (if Invert)
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// mov EAX = t1
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// lcs dest = [bitinstr.addr], t2 [EAX is implicit]
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// lcs dest = [bitinstr.addr], t3 [EAX is implicit]
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// bz newMBB
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// fallthrough -->nextMBB
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const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
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@@ -11353,13 +11354,6 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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for (int i=0; i <= lastAddrIndx; ++i)
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(*MIB).addOperand(*argOpers[i]);
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unsigned tt = F->getRegInfo().createVirtualRegister(RC);
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if (invSrc) {
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MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1);
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}
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else
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tt = t1;
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unsigned t2 = F->getRegInfo().createVirtualRegister(RC);
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assert((argOpers[valArgIndx]->isReg() ||
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argOpers[valArgIndx]->isImm()) &&
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@@ -11368,16 +11362,23 @@ X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr,
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MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2);
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else
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MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2);
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MIB.addReg(tt);
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MIB.addReg(t1);
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(*MIB).addOperand(*argOpers[valArgIndx]);
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unsigned t3 = F->getRegInfo().createVirtualRegister(RC);
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if (Invert) {
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MIB = BuildMI(newMBB, dl, TII->get(notOpc), t3).addReg(t2);
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}
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else
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t3 = t2;
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg);
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MIB.addReg(t1);
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MIB.addReg(t3);
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MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc));
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for (int i=0; i <= lastAddrIndx; ++i)
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(*MIB).addOperand(*argOpers[i]);
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MIB.addReg(t2);
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MIB.addReg(t3);
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assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand");
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(*MIB).setMemRefs(bInstr->memoperands_begin(),
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bInstr->memoperands_end());
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@@ -11400,7 +11401,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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unsigned regOpcH,
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unsigned immOpcL,
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unsigned immOpcH,
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bool invSrc) const {
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bool Invert) const {
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// For the atomic bitwise operator, we generate
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// thisMBB (instructions are in pairs, except cmpxchg8b)
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// ld t1,t2 = [bitinstr.addr]
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@@ -11408,6 +11409,7 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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// out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4)
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// op t5, t6 <- out1, out2, [bitinstr.val]
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// (for SWAP, substitute: mov t5, t6 <- [bitinstr.val])
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// neg t7, t8 < t5, t6 (if Invert)
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// mov ECX, EBX <- t5, t6
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// mov EAX, EDX <- t1, t2
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// cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit]
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@@ -11491,16 +11493,9 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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.addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB);
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// The subsequent operations should be using the destination registers of
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//the PHI instructions.
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if (invSrc) {
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t1 = F->getRegInfo().createVirtualRegister(RC);
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t2 = F->getRegInfo().createVirtualRegister(RC);
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg());
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg());
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} else {
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t1 = dest1Oper.getReg();
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t2 = dest2Oper.getReg();
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}
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// the PHI instructions.
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t1 = dest1Oper.getReg();
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t2 = dest2Oper.getReg();
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int valArgIndx = lastAddrIndx + 1;
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assert((argOpers[valArgIndx]->isReg() ||
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@@ -11527,15 +11522,26 @@ X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr,
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MIB.addReg(t2);
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(*MIB).addOperand(*argOpers[valArgIndx + 1]);
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unsigned t7, t8;
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if (Invert) {
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t7 = F->getRegInfo().createVirtualRegister(RC);
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t8 = F->getRegInfo().createVirtualRegister(RC);
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t7).addReg(t5);
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MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t8).addReg(t6);
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} else {
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t7 = t5;
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t8 = t6;
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}
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX);
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MIB.addReg(t1);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX);
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MIB.addReg(t2);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX);
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MIB.addReg(t5);
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MIB.addReg(t7);
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MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX);
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MIB.addReg(t6);
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MIB.addReg(t8);
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MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B));
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for (int i=0; i <= lastAddrIndx; ++i)
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@@ -855,7 +855,7 @@ namespace llvm {
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unsigned notOpc,
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unsigned EAXreg,
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const TargetRegisterClass *RC,
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bool invSrc = false) const;
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bool Invert = false) const;
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MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
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MachineInstr *BInstr,
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@@ -864,7 +864,7 @@ namespace llvm {
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unsigned regOpcH,
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unsigned immOpcL,
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unsigned immOpcH,
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bool invSrc = false) const;
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bool Invert = false) const;
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/// Utility function to emit atomic min and max. It takes the min/max
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/// instruction to expand, the associated basic block, and the associated
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@@ -13,6 +13,7 @@ entry:
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%xort = alloca i32 ; <i32*> [#uses=2]
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%old = alloca i32 ; <i32*> [#uses=18]
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%temp = alloca i32 ; <i32*> [#uses=2]
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%temp64 = alloca i64
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store i32 %argc, i32* %argc.addr
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store i8** %argv, i8*** %argv.addr
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store i32 0, i32* %val1
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@@ -106,6 +107,20 @@ entry:
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; CHECK: cmpxchgl
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%17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic
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store i32 %17, i32* %old
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; CHECK: andl
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; CHECK: notl
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; CHECK: lock
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; CHECK: cmpxchgl
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%18 = atomicrmw nand i32* %val2, i32 1401 monotonic
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store i32 %18, i32* %old
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; CHECK: andl
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; CHECK: andl
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; CHECK: notl
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; CHECK: notl
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; CHECK: lock
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; CHECK: cmpxchg8b
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%19 = atomicrmw nand i64* %temp64, i64 17361641481138401520 monotonic
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store i64 %19, i64* %temp64
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ret void
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}
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